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12-bit, 160 msps, 2/4/8 interpolating dual txdac+ ? d/a converter ad9773 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 12-bit resolution, 160 msps/400 msps input/output data rate selectable 2/4/8 interpolating filter programmable channel gain and offset adjustment f s /4, f s /8 digital quadrature modulation capability direct if transmission mode for 70 mhz + ifs enables image rejection architecture fully compatible spi? port excellent ac performance sfdr ?69 dbc @ 2 mhz to 35 mhz wcdma acpr ?69 db @ if = 19.2 mhz internal pll clock multiplier selectable internal clock divider versatile clock input differential/single-ended sine wave or ttl/cmos/lvpecl compatible versatile input data interface twos complement/straight binary data coding dual-port or single-port interleaved input data single 3.3 v supply operation power dissipation: typical 1.2 w @ 3.3 v on-chip 1.2 v reference 80-lead thermally enhanced tqfp package applications communications analog quadrature modulation architecture 3g, multicarrier gsm, tdma, cdma systems broadband wireless, point-to-point microwave radios instrumentation/ate general description the ad9773 1 is the 12-bit member of the ad977x pin compatible, high performance, programmable 2/4/8 interpolating txdac+ family. the ad977x family features a serial port interface (spi) that provides a high level of programmability, thus allowing for enhanced system-level options. these options include selectable 2/4/8 interpolation filters; f s /2, f s /4, or f s /8 digital quadrature modulation with image rejection; a direct if mode; programmable channel gain and offset control; programmable internal clock divider; straight binary or twos complement data interface; and a single-port or dual-port data interface. ( continued on page 4) 1 protected by u.s. patent numbers 5,568,145; 5,689,257; and 5,703,519. other patents pending. functional block diagram 02857-b-001 16 16 16 /2 16 16 16 16 16 /2 /2 /2 ad9773 data assembler i latch q latch mux control spi interface and control registers half-band filters also can be configured for "zero stuffing only" * i and q noninterleaved or interleaved data 12 12 clock out write select half- band filter1* filter bypass mux image rejection/ dual dac mode bypass mux i/q dac gain/offset registers half- band filter2* half- band filter3* cos idac idac vref ioffset gain dac differential clk offset dac cos i out prescaler pll clock multiplier and clock divider phase detector and vco sin sin f dac /2, 4, 8 ( f dac ) figure 1.
ad9773 rev. b | page 2 of 60 table of contents general description ......................................................................... 4 product highlights ....................................................................... 4 specifications..................................................................................... 5 absolute maximum ratings............................................................ 9 thermal characteristics .............................................................. 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 terminology .................................................................................... 12 typical performance characteristics ........................................... 13 mode control (via spi port) .................................................... 18 register description................................................................... 20 functional description.............................................................. 22 serial interface for register control ........................................ 22 general operation of the serial interface ............................... 22 instruction byte .......................................................................... 23 serial interface port pin descriptions ..................................... 23 msb/lsb transfers..................................................................... 23 notes on serial port operation ................................................ 25 dac operation........................................................................... 25 1r/2r mode ................................................................................ 26 clock input configurations ...................................................... 26 programmable pll .................................................................... 27 power dissipation....................................................................... 29 sleep/power-down modes........................................................ 29 two-port data input mode....................................................... 29 one-/two-port input modes.................................................... 30 pll enabled, two-port mode .................................................. 30 dataclk inversion.................................................................. 30 dataclk driver strength....................................................... 31 pll enabled, one-port mode .................................................. 31 oneportclk inversion......................................................... 31 iq pairing .................................................................................... 31 pll disabled, two-port mode ................................................. 32 pll disabled, one-port mode ................................................. 32 digital filter modes ................................................................... 32 amplitude modulation.............................................................. 33 modulation, no interpolation .................................................. 34 modulation, interpolation = 2 ............................................... 35 modulation, interpolation = 4 ............................................... 36 modulation, interpolation = 8 ............................................... 37 zero stuffing ............................................................................... 38 interpolating (complex mix mode) ........................................ 38 operations on complex signals............................................... 38 complex modulation and image rejection of baseband signals .......................................................................................... 39 image rejection and sideband suppression of modulated carriers ........................................................................................ 41 applying the ad9773 output configurations....................... 46 unbuffered differential output, equivalent circuit ............. 46 differential coupling using a transformer............................ 46 differential coupling using an op amp ................................ 47 interfacing the ad9773 with the ad8345 quadrature modulator.................................................................................... 47 evaluation board ........................................................................ 48 outline dimensions ....................................................................... 58 ordering guide .......................................................................... 58
ad9773 rev. b | page 3 of 60 revision history 4/04data sheet changed from rev. a to rev. b. update layout....................................................................universal changes to dc specifications ....................................................... 5 changes to absolute maximum ratings...................................... 9 changes to dac operation section........................................... 25 inserted figure 38.......................................................................... 25 changes to figure 40 .................................................................... 26 changes to table 11 ...................................................................... 28 changes to programmable pll section..................................... 29 changes to power dissipation section....................................... 29 changes to figures 49, 50, and 51 ............................................... 29 changes to pll enabled, one-port mode section................... 31 changes to pll disabled, one-port mode section.................. 32 changes to figure 102 .................................................................. 49 changes to figure 104 .................................................................. 50 updated ordering guide ............................................................. 58 updated outline dimensions...................................................... 58 3/03data sheet changed from rev. 0 to rev. a. edits to features ...............................................................................1 edits to dc specifications ..............................................................3 edits to dynamic specifications ....................................................4 edits to pin function descriptions ...............................................7 edits to table i ............................................................................... 14 edits to register descriptionaddress 02h section............... 15 edits to register descriptionaddress 03h section............... 16 edits to register descriptionaddress 07h, 0bh section ...... 16 edits to equation 1........................................................................ 16 edits to msb/lsb transfers section........................................... 18 changes to figure 8 ...................................................................... 20 edits to programmable pll section........................................... 21 added new figure 14.................................................................... 22 renumbered figures 15 through 69 ........................................... 22 add two-port data input mode section................................... 23 edits to pll enabled, two-port mode section......................... 24 edits to figure 19 .......................................................................... 24 edits to figure 21 .......................................................................... 25 edits to pll disabled, two-port mode section ....................... 25 edits to figure 22 .......................................................................... 25 edits to figure 23 .......................................................................... 26 edits to figure 26a ........................................................................ 27 edits to complex modulation and image rejection of baseband signals section............................................................................... 31 changes to figures 53 and 54...................................................... 38 edits to evaluation board section .............................................. 39 changes to figures 56 through 59 .............................................. 40 replaced figures figures 60 through 69 .................................... 42 updated outline dimensions...................................................... 49
ad9773 rev. b | page 4 of 60 general description (continued from page 1) the selectable 2/4/8 interpolation filters simplify the requirements of the reconstruction filters while simultaneously enhancing the txdac+ familys pass-band noise/distortion performance. the independent channel gain and offset adjust registers allow the user to calibrate lo feedthrough and sideband suppression errors associated with analog quadrature modulators. the 6 db of gain adjustment range can also be used to control the output power level of each dac. the ad9773 features the ability to perform f s /2, f s /4, and f s /8 digital modulation and image rejection when combined with an analog quadrature modulator. in this mode, the ad9773 accepts i and q complex data (representing a single or multicarrier waveform), generates a quadrature modulated if signal along with its orthogonal representation via its dual dacs, and presents these two reconstructed orthogonal if carriers to an analog quadrature modulator to complete the image rejection upconversion process. another digital modulation mode (i.e., the direct if mode) allows the original baseband signal representation to be frequency translated such that pairs of images fall at multiples of one-half the dac update rate. the ad977x family includes a flexible clock interface accepting differential or single-ended sine wave or digital logic inputs. an internal pll clock multiplier is included and generates the necessary on-chip high frequency clocks. it can also be disabled to allow the use of a higher performance external clock source. an internal programmable divider simplifies clock generation in the converter when using an external clock source. a flexible data input interface allows for straight binary or twos complement formats and supports single-port interleaved or dual-port data. dual high performance dac outputs provide a differential current output programmable over a 2 ma to 20 ma range. the ad9773 is manufactured on an advanced 0.35 micron cmos process, operates from a single supply of 3.1 v to 3.5 v, and consumes 1.2 w of power. targeted at a wide dynamic range, multicarrier, and multistandard systems, the superb baseband performance of the ad9773 is ideal for wide band cdma, multicarrier cdma, multicarrier tdma, multicarrier gsm, and high performance systems employing high order qam modulation schemes. the image rejection feature simplifies and can help to reduce the number of signal band filters need ed in a transmit signal chain. the direct if mode helps to eliminate a costly mixer stage for a variety of communications systems. product highlights 1. the ad9773 is the 12-bit member of the ad977x pin compatible, high performance, programmable 2/4/8 interpolating txdac+ family. 2. direct if transmission is possible for 70 mhz + ifs through a novel digital mixing process. 3. f s /2, f s /4, and f s /8 digital quadrature modulation and user selectable image rejection simplify/remove cascaded saw filter stages. 4. a 2/4/8 user selectable interpolating filter eases data rate and output signal reconstruction filter requirements. 5. user selectable twos complement/straight binary data coding. 6. user programmable channel gain control over 1 db range in 0.01 db increments. 7. user programmable channel offset control 10% over the fsr. 8. ultrahigh speed 400 msps dac conversion rate. 9. internal clock divider provides data rate clock for easy interfacing. 10. flexible clock input with single-ended or differential input, cmos, or 1 v p-p lo sine wave input capability. 11. low power: complete cmos dac operates on 1.2 w from a 3.1 v to 3.5 v single supply. the 20 ma full-scale current can be reduced for lower power operation, and several sleep functions reduce power during idle periods. 12. on-chip voltage reference: the ad9773 includes a 1.20 v temperature compensated band gap voltage reference. 13. 80-lead thermally enhanced tqfp.
ad9773 rev. b | page 5 of 60 specifications t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 1. dc specifications parameter min typ max unit resolution 12 bits dc accuracy 1 integral nonlinearity ?1.5 0.4 +1.5 lsb differential nonlinearity ?1 0.2 +1 lsb monotonicity guaranteed over specified temperature range analog output (for ir and 2r gain setting modes) offset error ?0.02 0.01 +0.02 % of fsr gain error (with internal reference) ?1.0 +1.0 % of fsr gain matching ?1.0 0.1 +1.0 % of fsr full-scale output current 2 2 20 ma output compliance range ?1.0 +1.25 v output resistance 200 k? output capacitance 3 pf gain, offset cal dacs, monoto nicity guaranteed reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 7 k? small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/c gain drift (with internal refere nce) 50 ppm of fsr/c reference voltage drift 50 ppm/c power supply avdd voltage range 3.1 3.3 3.5 v analog supply current (i avdd ) 4 72.5 76 ma i avdd in sleep mode 23.3 26 ma clkvdd voltage range 3.1 3.3 3.5 v clock supply current (i clkvdd ) 4 8.5 10.0 ma clkvdd (pll on) clock supply current (i clkvdd ) 23.5 ma dvdd voltage range 3.1 3.3 3.5 v digital supply current (i dvdd ) 4 34 41 ma nominal power dissipation 380 410 mw p dis 5 1.75 w p dis in pwdn 6.0 mw power supply rejection ratioavdd 0.4 % of fsr/v operating range ?40 +85 c 1 measured at i outa driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 ? the i ref current. 3 use an external amplifier to drive any external load. 4 100 msps f dac with f out = 1 mhz, all supplies = 3.3 v, no interpolation, no modulation. 5 400 msps f dac , f data = 50 msps, f s /2 modulation, pll enabled.
ad9773 rev. b | page 6 of 60 t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, pllvdd = 0 v, i outfs = 20 ma, interpolation = 2, differential transformer-coupled output, 50 ? doubly terminated, unless otherwise noted. table 2. dynamic specifications parameter min typ max unit dynamic performance maximum dac output update rate (f dac ) 400 msps output settling time (t st ) (to 0.025%) 11 ns output rise time (10% to 90%) 1 0.8 ns output fall time (10% to 90%) 1 0.8 ns output noise (i outfs = 20 ma) 50 pahz ac linearitybaseband mode spurious-free dynamic rang e (sfdr) to nyquist (f out = 0 dbfs) f data = 100 msps, f out = 1 mhz 70 84.5 dbc f data = 65 msps, f out = 1 mhz 83 dbc f data = 65 msps, f out = 15 mhz 79 dbc f data = 78 msps, f out = 1 mhz 83 dbc f data = 78 msps, f out = 15 mhz 77 dbc f data = 160 msps, f out = 1 mhz 75 dbc f data = 160 msps, f out = 15 mhz 77 dbc spurious-free dynamic range within a 1 mhz window f out = 0 dbfs, f data = 100 msps, f out = 1 mhz 72 92.6 dbc two-tone intermodulatio n (imd) to nyquist (f out1 = f out2 = ?6 dbfs) f data = 65 msps, f out1 = 10 mhz; f out2 = 11 mhz 80 dbc f data = 65 msps, f out1 = 20 mhz; f out2 = 21 mhz 75 dbc f data = 78 msps, f out1 = 10 mhz; f out2 = 11 mhz 80 dbc f data = 78 msps, f out1 = 20 mhz; f out2 = 21 mhz 75 dbc f data = 160 msps, f out1 = 10 mhz; f out2 = 11 mhz 80 dbc f data = 160 msps, f out1 = 20 mhz; f out2 = 21 mhz 75 dbc total harmonic distortion (thd) f data = 100 msps, f out = 1 mhz; 0 dbfs ?70 ?82.4 db signal to noise ratio (snr) f data = 78 msps, f out = 5 mhz; 0 dbfs 70 db f data = 160 msps, f out = 5 mhz; 0 dbfs 69 db adjacent channel power ratio (acpr) wcdma with 3.84 mhz bw, 5 mhz channel spacing if = baseband, f data = 76.8 msps 69 dbc if = 19.2 mhz, f data = 76.8 msps 69 dbc four-tone intermodulation 21 mhz, 22 mhz, 23 mhz, and 24 mhz at ?12 dbfs (f data = msps, missing center) 73 dbfs ac linearityif mode four-tone intermodulation at if = 200 mhz 201 mhz, 202 mhz, 203 mhz, and 204 mhz at -12 dbfs (f data = 160 msps, f dac = 320 mhz) 69 dbfs 1 measured single-ended into 50 ? load.
ad9773 rev. b | page 7 of 60 t min to t max , avdd = 3.3 v, clkvdd = 3.3 v, pllvdd = 0 v, dvdd = 3.3 v, i outfs = 20 ma, unless otherwise noted. table 3. digital specifications parameter min typ max unit digital inputs logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf clock inputs input voltage range 0 3 v common-mode voltage 0.75 1.5 2.25 v differential voltage 0.5 1.5 v serial control bus maximum sclk frequency (f slck ) 15 mhz mimimum clock pulse width high (t pwh ) 30 ns mimimum clock pulse width low (t pwl ) 30 ns maximum clock rise/fall time 1 ms minimum data/chip select setup time (t ds ) 25 ns minimum data hold time (t dh ) 0 ns maximum data valid time (t dv ) 30 ns reset pulse width 1.5 ns inputs (sdi, sdio, sclk, csb) logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current ?10 +10 a logic 0 current ?10 +10 a input capacitance 5 pf sdio output logic 1 voltage drvdd ? 0.6 v logic 0 voltage 0.4 v logic 1 current 30 50 ma logic 0 current 30 50 ma
ad9773 rev. b | page 8 of 60 digital filter specifications table 4. half-band filter no. 1 (43 coefficients) tap coefficient 1, 43 8 2, 42 0 3, 41 ?29 4, 40 0 5, 39 67 6, 38 0 7, 37 ?134 8, 36 0 9, 35 244 10, 34 0 11, 33 ?414 12, 32 0 13, 31 673 14, 30 0 15, 29 ?1,079 16, 28 0 17, 27 1,772 18, 26 0 19, 25 ?3,280 20, 24 0 21, 23 10,364 22 16,384 table 5. half-band filter no. 2 (19 coefficients) tap coefficient 1, 19 19 2, 18 0 3, 17 ?120 4, 16 0 5, 15 438 6, 14 0 7, 13 ?1,288 8, 12 0 9, 11 5,047 10 8,192 table 6. half-band filter no. 3 (11 coefficients) tap coefficient 1, 11 7 2, 10 0 3, 9 ?53 4, 8 0 5, 7 302 6 512 ?120 ?100 ?80 ?60 ?40 ?20 0 20 attenuation (dbfs) 02857-b-002 f out (normalized to input data rate) 0.5 0 1.0 1.5 2.0 figure 2. 2 interpolating filter response ?120 ?100 ?80 ?60 ?40 ?20 0 20 attenuation (dbfs) 02857-b-003 f out (normalized to input data rate) 0.5 0 1.0 1.5 2.0 figure 3. 4 interpolating filter response ?120 ?100 ?80 ?60 ?40 ?20 0 20 attenuation (dbfs) 02857-b-004 f out (normalized to input data rate) 2 0468 figure 4. 8 interpolating filter response
ad9773 rev. b | page 9 of 60 absolute maximum ratings table 7. parameter with respect to min max unit avdd, dvdd, clkvdd agnd, dgnd, clkgnd ?0.3 +4.0 v avdd, dvdd, clkvdd avdd, dvdd, clkvdd ?4.0 +4.0 v agnd, dgnd, clkgnd agnd, dgnd, clkgnd ?0.3 +0.3 v refio, fsadj1/fsadj2 agnd ?0.3 avdd + 0.3 v i outa , i outb agnd ?1.0 avdd + 0.3 v p1b11 to p1b0, p2b11 to p2b0 dgnd ?0.3 dvdd + 0.3 v dataclk, pll_lock dgnd ?0.3 dvdd + 0.3 v clk+, clkC, reset clkgnd ?0.3 clkvdd + 0.3 v lpf clkgnd ?0.3 clkvdd + 0.3 v spi_csb, spi_clk, spi_sdio, spi_sdo dgnd ?0.3 dvdd + 0.3 v junction temperature 125 c storage temperature ?65 +150 c lead temperature (10 sec) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. thermal characteristics thermal resistance 80-lead thermally enhanced tqfp package ja = 23.5c/w (with thermal pad soldered to pcb) esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9773 rev. b | page 10 of 60 pin configuration and fu nction descriptions 02857-b-005 80 79 78 77 76 71 70 69 68 67 66 65 75 74 73 72 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 12 17 18 20 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 clkvdd pin 1 identifier avdd avdd avdd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd avdd avdd avdd i outa1 i outa2 i outb2 i outb1 lpf clkvdd clkgnd clk+ clk? clkgnd dataclk/pll_lock dgnd dvdd p1b11 (msb) p1b10 p1b9 p1b8 p1b7 p1b6 dgnd dvdd p1b5 p1b4 nc = no connect fsadj1 fsadj2 refio reset spi_csb spi_clk spi_sdio spi_sdo dgnd dvdd nc nc nc nc p2b0 (lsb) p2b1 dgnd dvdd p2b2 p2b3 ad9773 txdac+ top view (not to scale) p1b3 p1b2 p1b1 p1b0 (lsb) dgnd dvdd nc nc nc nc iqsel/p2b11 (msb) oneportclk/p2b10 p2b9 p2b8 dgnd dvdd p2b7 p2b6 p2b5 p2b4 figure 5. pin configuration
ad9773 rev. b | page 11 of 60 table 8. pin function descriptions pin no. mnemonic description 1, 3 clkvdd clock supply voltage. 2 lpf pll loop filter. 4, 7 clkgnd clock supply common. 5 clk+ differential clock input. 6 clkC differential clock input. 8 dataclk/pll_lock with the pll enabled, this pin indicates the stat e of the pll. a read of a logic 1 indicates the pll is in the locked state. logic 0 indicates the pll has not achieved lock. this pin may also be programmed to act as either an input or outp ut (address 02h, bit 3) dataclk signal running at the input data rate. 9, 17, 25, 35, 44, 52 dgnd digital common. 10, 18, 26, 36, 43, 51 dvdd digital supply voltage. 11 to 16, 19 to 24, p1b11 (msb) to p1b0 (lsb) port 1 data inputs. 27 to 30, 47 to 50 nc no connect. 31 iqsel/p2b11 (msb) in one-port mode, iqsel = 1 followed by a rising edge of the differential input clock will latch the data into the i channel input register. iq sel = 0 will latch the data into the q channel input register. in two-port mode, th is pin becomes the port 2 msb. 32 oneportclk/p2b10 with the pll disabled and the ad9773 in one-po rt mode, this pin becomes a clock output that runs at twice the input data rate of the i and q channels. this allows the ad9773 to accept and demux interleaved i and q da ta to the i and q input registers. 33, 34, 37 to 42, 45, 46 p2b9 to p2b0 (lsb) port 2 data inputs. 53 spi_sdo in the case where sdio is an input, sdo acts as an output. when sd io becomes an output, sdo enters a high-z state. this pin can also be used as an output for th e data rate clock. for more information, see the two-po rt data input mode section. 54 spi_sdio bidirectional data pin. data direction is cont rolled by bit 7 of register address 00h. the default setting for this bit is 0, which sets sdio as an input. 55 spi_clk data input to the spi port is registered on the ri sing edge of spi_clk. data output on the spi port is registered on the falling edge. 56 spi_csb chip select/spi data synchronization. on mo mentary logic high, resets spi port logic and initializes instruction cycle. 57 reset logic 1 resets all of the spi port registers, in cluding address 00h, to their default values. a software reset can also be done by writing a logic 1 to spi register 00h, bit 5. however, the software reset has no effect on the bits in address 00h. 58 refio reference output, 1.2 v nominal. 59 fsadj2 full-scale curre nt adjust, q channel. 60 fsadj1 full-scale curre nt adjust, i channel. 61, 63, 65, 76, 78, 80 avdd analog supply voltage. 62, 64, 66, 67, 70, 71, 74, 75, 77, 79 agnd analog common. 68, 69 i outb2 , i outa2 differential dac current outputs, q channel. 72, 73 i outb1 , i outa1 differential dac current outputs, i channel.
ad9773 rev. b | page 12 of 60 terminology adjacent channel power ratio (acpr) a ratio, in dbc, between the measured power within a channel relative to its adjacent channel. complex image rejection in a traditional two-part upconversion, two images are created around the second if frequency. these images are redundant and have the effect of wasting transmitter power and system bandwidth. by placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second if can be rejected. complex modulation the process of passing the real and imaginary components of a signal through a complex modulator (transfer function = e jt = cost + jsint) and realizing real and imaginary components on the modulator output. differential nonlinearity (dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. group delay number of input clocks between an impulse applied at the device input and the peak dac output current. a half-band fir filter has constant group delay over its entire frequency range. impulse response response of the device to an impulse applied to the input. interpolation filter if the digital inputs to the dac are sampled at a multiple rate of f data (interpolation rate), a digital filter can be constructed with a sharp transition band near f data /2. images that would typically appear around f dac (output data rate) can be greatly suppressed. linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. monotonicity a dac is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of 0 is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1.s output compliance range the range of allowable voltage at the output of a current output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. pass band frequency band in which any input applied therein passes unattenuated to the dac output. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. stop-band rejection the amount of attenuation of a frequency outside the pass band applied to the dac, relative to a full-scale signal applied at the dac input within the pass band. temperature drift it is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db).
ad9773 rev. b | page 13 of 60 typical performance characteristics t = 25c, avdd = 3.3 v, clkvdd = 3.3 v, dvdd = 3.3 v, i outfs = 20 ma, interpolation = 2, differential transformer-coupled output, 50 ? doubly terminated, unless otherwise noted. ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 amplitude (dbm) 02857-b-006 frequency (mhz) 0 65 130 figure 6. single-tone spectrum @ f data = 65 msps with f out = f data /3 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-007 frequency (mhz) 020 10 30 ?12dbfs ?6dbfs 0dbfs figure 7. in-band sfdr vs. f out @ f data = 65 msps 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-008 frequency (mhz) 020 10 30 ?12dbfs ?6dbfs 0dbfs figure 8. out-of-band sfdr vs. f out @ f data = 65 msps ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 amplitude (dbm) 02857-b-009 frequency (mhz) 0 100 50 150 figure 9. single-tone spectrum @ f data = 78 msps with f out = f data /3 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-010 frequency (mhz) 020 10 30 ?12dbfs ?6dbfs 0dbfs figure 10. in-band sfdr vs. f out @ f data = 78 msps 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-011 frequency (mhz) 020 10 30 ?12dbfs ?6dbfs 0dbfs figure 11. out-of-band sfdr vs. f out @ f data = 78 msps
ad9773 rev. b | page 14 of 60 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 amplitude (dbm) 02857-b-012 frequency (mhz) 0 200 100 300 figure 12. single-tone spectrum @ f data = 160 msps with f out = f data /3 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-013 01020304050 frequency (mhz) ?12dbfs 0dbfs ?6dbfs figure 13. in-band sfdr vs. f out @ f data = 160 msps 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-014 0 1020304050 frequency (mhz) ?12dbfs 0dbfs ?6dbfs figure 14. out-of-band sfdr vs. f out @ f data = 160 msps 50 55 60 65 70 75 imd (dbc) 80 85 90 02857-b-015 frequency (mhz) 020 10 30 ?3dbfs ?6dbfs 0dbfs figure 15. third-order imd products vs. f out @ f data = 65 msps 50 55 60 65 70 75 imd (dbc) 80 85 90 02857-b-016 frequency (mhz) 020 10 30 ?3dbfs ?6dbfs 0dbfs figure 16. third-order imd products vs. f out @ f data = 78 msps 50 55 60 65 70 75 imd (dbc) 80 85 90 02857-b-017 frequency (mhz) 040 20 60 ?3dbfs ?6dbfs 0dbfs figure 17. third-order imd products vs. f out @ f data = 160 msps
ad9773 rev. b | page 15 of 60 50 55 60 65 70 75 imd (dbc) 80 85 90 02857-b-018 frequency (mhz) 040 20 60 1 2 8 4 figure 18. third-order imd products vs. f out and interpolation rate, 1 f data = 160 msps, 2 f data = 160 msps, 4 f data = 80 msps, 8 f data = 50 msps 50 55 60 65 70 75 imd (dbc) 80 85 90 02857-b-019 a out (dbfs) ?15 ?5 ?10 0 1 2 8 4 figure 19. third-order imd products vs. a out and interpolation rate, f data = 50 msps for all cases, 1 f dac = 50 msps, 2 f dac = 100 msps, 4 f dac = 200 msps, 8 f dac = 400 msps 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-020 avdd (v) 3.2 3.1 3.3 3.4 3.5 0dbfs ?12dbfs ?6dbfs figure 20. sfdr vs. avdd @: f out = 10 mhz, f dac = 320 msps, f data = 160 msps 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-021 avdd (v) 3.2 3.1 3.3 3.4 3.5 0dbfs ?3dbfs ?6dbfs figure 21. third-order imd products vs. avdd @ f out = 10 mhz, f dac = 320 msps, f data = 160 msps 50 55 60 65 70 75 snr (db) 80 85 90 02857-b-022 input data rate (msps) 0 150 pll off pll on 0 100 50 150 figure 22. snr vs. data rate for f out = 5 mhz 50 55 60 65 70 75 sfdr (dbc) 80 85 90 02857-b-023 temperature (c) ?50 50 0 100 f data = 65msps 160msps 78msps figure 23. sfdr vs. temperature @ f out = f data /11
ad9773 rev. b | page 16 of 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-024 frequency (mhz) 0 100 50 figure 24. single-tone spurious performance, f out = 10 mhz, f data = 150 msps, no interpolation ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-025 frequency (mhz) 10 0203040 figure 25. two-tone imd performance, f data = 150 msps, no interpolation ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-026 0 50 100 150 200 250 frequency (mhz) figure 26. single-tone spurious performance, f out = 10 mhz, f data = 150 msps, interpolation = 2 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbm) 20 15 510 025303540 frequency (mhz) 02857-b-027 figure 27. two-tone imd performance, f data = 150 msps, interpolation = 4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-028 0 50 100 150 200 250 frequency (mhz) figure 28. single-tone spurious performance, f out = 10 mhz, f data = 80 msps, interpolation = 4 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbm) 02857-b-029 0 5 10 15 20 25 frequency (mhz) figure 29. two-tone imd performance, f out = 10 mhz, f data = 50 msps, interpolation = 8
ad9773 rev. b | page 17 of 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-030 frequency (mhz) 0 200 100 300 figure 30. single-tone spurious performance, f out = 10 mhz, f data = 50 msps, interpolation = 8 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-031 frequency (mhz) 040 20 60 figure 31. eight-tone imd performance, f data = 160 msps, interpolation = 8
ad9773 rev. b | page 18 of 60 mode control (via spi port) table 9. mode control via spi port (default values are highlighted) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h sdio bidirectional 0 = input 1 = i/o lsb, msb first 0 = msb 1 = lsb software reset on logic 1 sleep mode logic 1 shuts down the dac output currents. power-down mode logic 1 shuts down all digital and analog functions. 1r/2r mode dac output current set by one or two external resistors. 0 = 2r, 1 = 1r pll_lock indicator 01h filter interpolation rate (1, 2, 4, 8) filter interpolation rate (1, 2, 4, 8) modulation mode ( none , f s /2, f s /4, f s /8) modulation mode ( none , f s /2, f s /4, f s /8) 0 = no zero stuffing on interpolation filters , logic 1 enables zero stuffing. 1 = real mix mode 0 = complex mix mode 0 = e Cjt 1 = e +jt dataclk/ pll_lock 1 select 0 = plllock 1 = dataclk 02h 0 = signed input data 1 = unsigned 0 = two-port mode 1 = one-port mode dataclk driver strength dataclk invert 0 = no invert 1 = invert oneportclk invert 0 = no invert 1 = invert iqsel invert 0 = no invert 1 = invert q first 0 = i first 1 = q first 03h data rate 1 output clock pll divide (prescaler) ratio pll divide (prescaler) ratio 04h 0 = pll off 1 1 = pll on 0 = automatic charge pump control 1 = programmable pll charge pump control pll charge pump control pll charge pump control 05h idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment idac fine gain adjustment 06h idac coarse gain adjustment idac coarse gain adjustment idac coarse gain adjustment idac coarse gain adjustment 07h idac offset adjustment bit 9 idac offset adjustment bit 8 idac offset adjustment bit 7 idac offset adjustment bit 6 idac offset adjustment bit 5 idac offset adjustment bit 4 idac offset adjustment bit 3 idac offset adjustment bit 2 08h idac i offset direction 0 = i offset on i outa 1 = i offset on i outb idac offset adjustment bit 1 idac offset adjustment bit 0 09h qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment qdac fine gain adjustment 1 see the two-port data input mode section for more information.
ad9773 rev. b | page 19 of 60 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0ah qdac coarse gain adjustment qdac coarse gain adjustment qdac coarse gain adjustment qdac coarse gain adjustment 0bh qdac offset adjustment bit 9 qdac offset adjustment bit 8 qdac offset adjustment bit 7 qdac offset adjustment bit 6 qdac offset adjustment bit 5 qdac offset adjustment bit 4 qdac offset adjustment bit 3 qdac offset adjustment bit 2 0ch qdac i offset direction 0 = i offset on i outa 1 = i offset on i outb qdac offset adjustment bit 1 qdac offset adjustment bit 0 0dh version register version register version register version register
ad9773 rev. b | page 20 of 60 register description address 00h bit 7 : logic 0 (default). causes the spi_sdio pin to act as an input during the data transfer (phase 2) of the communications cycle. when set to 1, spi_sdio can act as an input or output, depending on bit 7 of the instruction byte. bit 6 : logic 0 (default). determines the direction (lsb/msb first) of the communications and data transfer communications cycles. refer to the msb/lsb transfers section for more details. bit 5 : writing a 1 to this bit resets the registers to their default values and restarts the chip. the reset bit always reads back 0. register address 00h bits are not cleared by this software reset. however, a high level at the reset pin forces all registers, including those in address 00h, to their default state. bit 4 : sleep mode. a logic 1 to this bit shuts down the dac output currents. bit 3 : power-down mode. logic 1 shuts down all analog and digital functions except for the spi port. bit 2 : 1r/2r mode. the default (0) places the ad9773 in two resistor mode. in this mode, the i ref currents for the i and q dac references are set separately by the r set resistors on fsadj1 and fsadj2 (pins 59 and 60). in 2r mode, assuming the coarse gain setting is full scale and the fine gain setting is zero, i fullscale1 = 32 v ref /fsadj1 and i fullscale2 = 32 v ref /fsadj2. with this bit set to 1, the reference currents for both i and q dacs are controlled by a single resistor on pin 60. i fullscale in one resistor mode for both i and q dacs is half of what it would be in 2r mode, assuming all other conditions (r set , register settings) remain unchanged. the full-scale current of each dac can still be set to 20 ma by choosing a resistor of half the value of the r set value used in 2r mode. bit 1 : pll_lock indicator. when the pll is enabled, reading this bit will give the status of the pll. a logic 1 indicates the pll is locked. a logic 0 indicates an unlocked state. address 01h bits 7, 6 : this is the filter interpolation rate according to the following table. 00 1 01 2 10 4 11 8 bits 5, 4 : this is the modulation mode according to the following table. 00 none 01 f s /2 10 f s /4 11 f s /8 bit 3 : logic 1 enables zero stuffing mode for interpolation filters. bit 2 : default (1) enables the real mix mode. the i and q data channels are individually modulated by f s /2, f s /4, or f s /8 after the interpolation filters. however, no complex modulation is done. in the complex mix mode (logic 0), the digital modulators on the i and q data channels are coupled to create a digital complex modulator. when the ad9773 is applied in conjunction with an external quadrature modulator, rejection can be achieved of either the higher or lower frequency image around the second if frequency (i.e., the lo of the analog quadrature modulator external to the ad9773) according to the bit value of register 01h, bit 1. bit 1 : logic 0 (default) causes the complex modulation to be of the form e ?jt , resulting in the rejection of the higher frequency image when the ad9773 is used with an external quadrature modulator. a logic 1 causes the modulation to be of the form e +jt , which causes rejection of the lower frequency image. bit 0 : in two-port mode, a logic 0 (default) causes pin 8 to act as a lock indicator for the internal pll. a logic 1 in this register causes pin 8 to act as a dataclk. for more information, see the two-port data input mode section. address 02h bit 7 : logic 0 (default) causes data to be accepted on the inputs as twos complement. logic 1 causes data to be accepted as straight binary. bit 6 : logic 0 (default) places the ad9773 in two-port mode. i and q data enters the ad9773 via ports 1 and 2, respectively. a logic 1 places the ad9773 in one-port mode in which interleaved i and q data is applied to port 1. see table 8 for detailed information on how the dataclk/pll_lock, iqsel, and oneportclk modes. bit 5 : dataclk driver strength. with the internal pll disabled and this bit set to logic 0, it is recommended that dataclk be buffered. when this bit is set to logic 1, dataclk acts as a stronger driver capable of driving small capacitive loads. bit 4 : default logic 0. a value of 1 inverts dataclk at pin 8. bit 2 : default logic 0. a value of 1 inverts oneportclk at pin 32. bit 1 : the default of logic 0 causes iqsel = 0 to direct input data to the i channel, while iqsel = 1 directs input data to the q channel.
ad9773 rev. b | page 21 of 60 bit 0 : the default of logic 0 defines iq pairing as iq, iq, ... while programming a logic 1 causes the pair ordering to be qi, qi, ... address 03h bit 7 : allows the data rate clock (divided down from the dac clock) to be output at either the dataclk pin (pin 8) or at the spi_sdo pin (pin 53). the default of 0 in this bit will enable the data rate clock at dataclk, while a 1 in this bit will cause the data rate clock to be output at spi_sdo. for more information, see the two-port data input mode section. bits 1, 0: setting this divide ratio to a higher number allows the vco in the pll to run at a high rate (for best performance), while the dac input and output clocks run substantially slower. the divider ratio is set according to the following table. 00 1 01 2 10 4 11 8 address 04h bit 7 : logic 0 (default) disables the internal pll. logic 1 enables the pll. bit 6 : logic 0 (default) sets the charge pump control to automatic. in this mode, the charge pump bias current is controlled by the divider ratio defined in address 03h, bits 1 and 0. logic 1 allows the user to manually define the charge pump bias current using address 04h, bits 2, 1, and 0. adjusting the charge pump bias current allows the user to optimize the noise/settling performance of the pll. bits 2, 1, 0 : with the charge pump control set to manual, these bits define the charge pump bias current according to the following table. 000 50 a 001 100 a 010 200 a 011 400 a 111 800 a address 05h, 09h bits 7 to 0 : these bits represent an 8-bit binary number (bit 7 msb) that defines the fine gain adjustment of the i (05h) and q (09h) dac according to equation 1. address 06h, 0ah bits 3 to 0 : these bits represent a 4-bit binary number (bit 3 msb) that defines the coarse gain adjustment of the i (06h) and q (0ah) dacs according to equation 1. address 07h, 0bh bits 7 to 0 : these bits are used in conjunction with address 08h, 0ch, bits 1, 0. address 08h, 0ch bits 1, 0 : the 10 bits from these two address pairs (07h, 08h and 0bh, 0ch) represent a 10-bit binary number that defines the offset adjustment of the i and q dacs according to the equation below: (07h, 0bh: bit 7 msb; 08h, 0ch: bit 0 lsb). address 08h, 0ch bit 7 : this bit determines the direction of the offset of the i (08h) and q (0ch) dacs. a logic 0 will apply a positive offset current to i outa , while a logic 1 will apply a positive offset current to i outb . the magnitude of the offset current is defined by the bits in addresses 07h, 0bh, 08h, and 0ch according to equation 1. equation 1 shows i outa and i outb as a function of fine gain, coarse gain, and offset adjustment when using 2r mode. in 1r mode, the current i ref is created by a single fsadj resistor (pin 60). this current is divided equally into each channel so that a scaling factor of one-half must be added to these equations for full-scale currents for both dacs and the offset. ) ( 1024 4 ) ( 2 1 2 24 1024 256 32 3 16 1 8 6 ) ( 2 24 1024 256 32 3 16 1 8 6 12 12 12 a offset i i a data fine i coarse i i a data fine i coarse i i ref offset ref ref outb ref ref outa ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = (1)
ad9773 rev. b | page 22 of 60 functional description the ad9773 dual interpolating dac consists of two data channels that can be operated completely independently or coupled to form a complex modulator in an image reject transmit architecture. each channel includes three fir filters, making the ad9773 capable of 2, 4, or 8 interpolation. high speed input and output data rates can be achieved within the following limitations. interpolation rate (msps) input data rate (msps) dac sample rate (msps) 1 160 160 2 160 320 4 100 400 8 50 400 both data channels contain a digital modulator capable of mixing the data stream with an lo of f dac /2, f dac /4, or f dac /8, where f dac is the output data rate of the dac. a zero stuffing feature is also included and can be used to improve pass-band flatness for signals being attenuated by the sin(x)/x characteristic of the dac output. the speed of the ad9773, combined with its digital modulation capability, enables direct if conversion architectures at 70 mhz and higher. the digital modulators on the ad9773 can be coupled to form a complex modulator. by using this feature with an external analog quadrature modulator, such as analog devices ad8345, an image rejection architecture can be enabled. to optimize the image rejection capability, as well as lo feedthrough in this architecture, the ad9773 offers programmable (via the spi port) gain and offset adjust for each dac. also included on the ad9773 are a phase-locked loop (pll) clock multiplier and a 1.20 v band gap voltage reference. with the pll enabled, a clock applied to the clk+/clk? inputs is frequency multiplied internally and generates all necessary internal synchronization clocks. each 12-bit dac provides two complementary current outputs whose full-scale currents can be determined either from a single external resistor or independently from two separate resistors (see the 1r/2r mode section). the ad9773 features a low jitter, differential clock input that provides excellent noise rejection while accepting a sine or square wave input. separate voltage supply inputs are provided for each functional block to ensure optimum noise and distortion performance. sleep and power-down modes can be used to turn off the dac output current (sleep) or the entire digital and analog sections (power-down) of the chip. an spi compliant serial port is used to program the many features of the ad9773. note that in power-down mode, the spi port is the only section of the chip still active. sdo (pin 53) sdio (pin 54) sclk (pin 55) csb (pin 56) ad9773 spi port interface 02857-b-032 figure 32. spi port interface serial interface for register control the ad9773 serial port is a flexible, synchronous serial communications port that allows easy interface to many industry-standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola spi and intel ssr protocols. the interface allows read/write access to all registers that configure the ad9773. single- or multiple-byte transfers are supported as well as msb first or lsb first transfer formats. the ad9773s serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for i/o (sdio/sdo). general operation of the serial interface there are two phases to a communication cycle with the ad9773. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9773 coincident with the first eight sclk rising edges. the instruction byte provides the ad9773 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9773. a logic 1 on the spi_csb pin, followed by a logic low, will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the middle of an instruction cycle or a data transfer cycle, none of the present data will be written. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9773 and the system controller. phase 2 of the communication cycle is a transfer of one to four data bytes, as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires one byte only. registers change immediately upon writing to the last bit of each transfer byte.
ad9773 rev. b | page 23 of 60 instruction byte the instruction byte contains the information shown below. n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 bytes 1 0 transfer 3 bytes 1 1 transfer 4 bytes r/w bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. logic 1 indicates read operation. logic 0 indicates a write operation. n1, n0 bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the following table. msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 a4, a3, a2, a1, and a0 bits 4, 3, 2, 1, and 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9773. serial interface port pin descriptions spi_clk (pin 55)serial clock the serial clock pin is used to synchronize data to and from the ad9773 and to run the internal state machines. the spi_clk maximum frequency is 15 mhz. all data input to the ad9773 is registered on the rising edge of spi_clk. all data is driven out of the ad9773 on the falling edge of spi_clk. spi_csb (pin 56)chip select active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications lines. the spi_sdo and spi_sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. spi_sdio (pin 54)serial data i/o data is always written into the ad9773 on this pin. however, this pin can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 00h. the default is logic 0, which configures the sdio pin as unidirectional. spi_sdo (pin 53)serial data out data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9773 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the ad9773 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the first lsb bit in register 0. the default is msb first. when this bit is set active high, the ad9773 serial port is in lsb first format. in lsb first mode, the instruction byte and data bytes must be written from lsb to msb. in lsb first mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. when this bit is set default low, the ad9773 serial port is in msb first format. in msb first mode, the instruction byte and data bytes must be written from msb to lsb. in msb first mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. when incrementing from 1fh, the address generator changes to 00h. when decrementing from 00h, the address generator changes to 1fh.
ad9773 rev. b | page 24 of 60 instruction cycle data transfer cycle cs s cl k sdio sdo r/w i4 i3 i2 i1 i0 d7 n d6 n d7 n d6 n d2 0 d1 0 d0 0 d2 0 d1 0 d0 0 i6 (n) i5 (n) 02857-b-033 figure 33. serial register interface timing msb first 02857-b-034 cs s clk sdio sdo instruction cycle data transfer cycle i0 i1 i2 i3 i4 i5 (n) i6 (n) r/w d0 0 d1 0 d2 0 d6 n d7 n d0 0 d1 0 d2 0 d6 n d7 n figure 34. serial register interface timing lsb first t 02857-b-035 cs sclk sdio t ds t sclk t pwh t ds t dh t pwl instruction bit 7 instruction bit 6 figure 35. timing diagram for register write to ad9773 cs sclk sdio sdo data bit n t dv data bit n?1 02857-b-036 figure 36. timing diagram for register read from ad9773
ad9773 rev. b | page 25 of 60 notes on serial port operation the ad9773 serial port configuration bits reside in bits 6 and 7 of register address 00h. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of the communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. the same considerations apply to setting the reset bit in register address 00h. all other registers are set to their default values, but the software reset does not affect the bits in register address 00h. it is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset. a write to bits 1, 2, and 3 of address 00h with the same logic levels as for bits 7, 6, and 5 (bit pattern: xy1001yx binary) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. a second write to address 00h with reset bit low and serial port configuration as specified above (xy) reprograms the osc in multiplier setting. a changed f sysclk frequency is stable after a maximum of 200 f mclk cycles (equals wake-up time). dac operation the dual 12-bit dac output of the ad9773, along with the reference circuitry, gain, and offset registers, is shown in figure 37 and figure 38 . note that an external reference can be used by simply overdriving the internal reference with the external reference. referring to the transfer functions in equation 1, a reference current is set by the internal 1.2 v reference, the external r set resistor, and the values in the coarse gain register. the fine gain dac subtracts a small amount from this and the result is input to idac and qdac, where it is scaled by an amount equal to 1024/24. figure 39 and figure 40 show the scaling effect of the coarse and fine adjust dacs. idac and qdac are pmos current source arrays, segmented in a 5-4-3 configuration. the five most significant bits control an array of 31 current sources. the next four bits consist of 15 current sources whose values are all equal to 1/16 of an msb current source. the three lsbs are binary weighted fractions of the middle bits current sources. all current sources are switched to either i outa or i outb , depending on the input code. the fine adjustment of the gain of each channel allows for improved balance of qam modulated signals, resulting in improved modulation accuracy and image rejection. in the interfacing the ad9773 with the ad8345 quadrature modulator section, the performance data shows to what degree image rejection can be improved when the ad9773 is used with an ad8345 quadrature modulator from adi. fine gain dac fine gain dac coarse gain dac coarse gain dac offset dac offset dac gain control registers offset control registers gain control registers offset control registers 1.2vref idac qdac refio 0.1 f fsadj1 rset1 i outa1 i outa2 i outb1 i outb2 rset2 fsadj2 02857-b-037 figure 37. dac outputs, reference current scaling, and gain/offset adjust 02857-b-038 8 4 a 7k ? 0.7v refio avdd figure 38. internal reference equivalent circuit 2r mode 1r mode 0 5 10 15 20 25 coarse reference current (ma) 02857-b-039 coarse gain register code (assuming rset1, rset2 = 1.9k ? ) 5 0101520 figure 39. coarse gain effect on i fullscale
ad9773 rev. b | page 26 of 60 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 fine reference current (ma) 02857-b-040 0 1r mode 2r mode fine gain register code (assuming rset1, rset2 = 1.9k ? ) 200 400 600 800 1000 figure 40. fine gain effect on i fullscale the offset control defines a small current that can be added to i outa or i outb (not both) on the idac and qdac. the selection of which i out this offset current is directed toward is programmable via register 08h, bit 7 (idac) and register 0ch, bit 7 (qdac). figure 41 shows the scale of the offset current that can be added to one of the complementary outputs on the idac and qdac. offset control can be used for suppression of lo leakage resulting from modulation of dc signal components. if the ad9773 is dc-coupled to an external modulator, this feature can be used to cancel the output offset on the ad9773 as well as the input offset on the modulator. figure 42 shows a typical example of the effect that the offset control has on lo suppression. in figure 42, the negative scale represents an offset added to i outb , while the positive scale represents an offset added to i outa of the respective dac. offset register 1 corresponds to idac, while offset register 2 corresponds to qdac. figure 42 represents the ad9773 synthesizing a complex signal that is then dc-coupled to an ad8345 quadrature modulator with an lo of 800 mhz. the dc-coupling allows the input offset of the ad8345 to be calibrated out as well. the lo suppression at the ad8345 output was optimized first by adjusting offset register 1 in the ad9773. when an optimal point was found (roughly code 54), this code was held in offset register 1, and offset register 2 was adjusted. the resulting lo suppression is 70 dbfs. these are typical numbers, and the specific code for optimization will vary from part to part. 0 1 2 3 4 5 offset current (ma) 02857-b-041 0 coarse gain register code (assuming rset1, rset2 = 1.9k ? ) 2r mode 1r mode 0 200 400 600 800 1000 figure 41. dac output offset current ?80 ?70 ?60 ?50 ?40 ?30 lo suppression (dbfs) ?20 ?10 0 0 ?256 ?768 ?512 ?1024 256 512 768 1024 dac1, dac2 (offset register codes) 02857-b-042 offset register 1 adjusted offset register 2 adjusted, with offset register 1 set to optimized value figure 42. offset adjust control, effect on lo suppression 1r/2r mode in 2r mode, the reference current for each channel is set independently by the fsadj resistor on that channel. the ad9773 can be programmed to derive its reference current from a single resistor on pin 60 by putting the part into 1r mode. the transfer functions in equation 1 are valid for 2r mode. in 1r mode, the current developed in the single fsadj resistor is split equally between the two channels. the result is that in 1r mode, a scale factor of 1/2 must be applied to the formulas in equation 1. the full-scale dac current in 1r mode can still be set to as high as 20 ma by using the internal 1.2 v reference and a 950 ? resistor instead of the 1.9 k? resistor typically used in 2r mode. clock input configurations the clock inputs to the ad9773 can be driven differentially or single-ended. the internal clock circuitry has supply and ground (clkvdd, clkgnd) separate from the other supplies on the chip to minimize jitter from internal noise sources.
ad9773 rev. b | page 27 of 60 figure 43 shows the ad9773 driven from a single-ended clock source. the clk+/clk? pins form a differential input (clkin) so that the statically terminated input must be dc- biased to the midswing voltage level of the clock driven input. 02857-b-043 ad9773 r series clk+ clk? 0.1 f clkvdd clkgnd v threshold figure 43. single-ended clock driving clock inputs a configuration for differentially driving the clock inputs is given in figure 44. dc-blocking capacitors can be used to couple a clock driver output whose voltage swings exceed clkvdd or clkgnd. if the driver voltage swings are within the supply range of the ad9773, the dc-blocking capacitors and bias resistors are not necessary. 02857-b-044 ad9773 clk+ 0.1 f 0.1 f 0.1 f 1k ? 1k ? 1k ? 1k ? ecl/pecl clk? clkvdd clkgnd figure 44. differential clock driving clock inputs a transformer, such as the t1-1t from mini-circuits, can also be used to convert a single-ended clock to differential. this method is used on the ad9773 evaluation board so that an external sine wave with no dc offset can be used as a differential clock. pecl/ecl drivers require varying termination networks, the details of which are left out of figure 43 and figure 44 but can be found in application notes such as the and8020/d from on semiconductor. these networks depend on the assumed transmission line impedance and power supply voltage of the clock driver. optimum performance of the ad9773 is achieved when the driver is placed very close to the ad9773 clock inputs, thereby negating any transmission line effects such as reflections due to mismatch. the quality of the clock and data input signals is important in achieving optimum performance. the external clock driver circuitry should provide the ad9773 with a low jitter clock input that meets the minimum/maximum logic levels while providing fast edges. although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain bandwidth product of the ad9773s clock input comparator can tolerate differential sine wave inputs as low as 0.5 v p-p, with minimal degradation of the output noise floor. programmable pll clkin can function either as an input data rate clock (pll enabled) or as a dac data rate clock (pll disabled) according to the state of address 02h, bit 7 in the spi port register. the internal operation of the ad9773 clock circuitry in these two modes is illustrated in figure 45 and figure 46. the pll clock multiplier and distribution circuitry produce the necessary internal synchronized 1, 2, 4, and 8 clocks for the rising edge triggered latches, interpolation filters, modulators, and dacs. this circuitry consists of a phase detector, charge pump, voltage controlled oscillator (vco), prescaler, clock distribution, and spi port control. the charge pump, vco, differential clock input buffer, phase detector, prescaler, and clock distribution are all powered from clkvdd. pll lock status is indicated by the logic signal at the dataclk_pll_lock pin, as well as by the status of bit 1, register 00h. to ensure optimum phase noise performance from the pll clock multiplier and distribution, clkvdd should originate from a clean analog supply. the vco speed is a function of the input data rate, the interpolation rate, and the vco prescaler, according to the following function: ( ) () escaler pr ionrate interpolat mhz rate data input mhz speed vco = table 10 defines the minimum input data rates versus the interpolation and pll divider setting. if the input data rate drops below the defined minimum under these conditions, vco phase noise may increase significantly. ad9773 pllvdd input data latches pll_lock 1 = lock 0 = no lock spi port lpf clk+ clk? interpolation filters, modulators, and dacs clock distribution circuitry interpolation rate control internal spi control registers modulation rate control pll control (pll on) pll divider (prescaler) control prescaler vco phase detector charge pump 2 1 48 02857-b-045 figure 45. pll and clock ci rcuitry with pll enabled
ad9773 rev. b | page 28 of 60 ad9773 input data latches pll_lock 1 = lock 0 = no lock spi port clk+ clk? interpolation filters, modulators, and dacs clock distribution circuitry interpolation rate control internal spi control registers modulation rate control pll control (pll on) pll divider (prescaler) control prescaler vco phase detector charge pump 2 1 48 02857-b-046 figure 46. pll and clock ci rcuitry with pll disabled in addition, if the zero stuffing option is enabled, the vco will double its speed again. phase noise may be slightly higher with the pll enabled. figure 47 illustrates typical phase noise performance of the ad9773 with 2 interpolation and various input data rates. the signal synthesized for the phase noise measurement was a single carrier at a frequency of f data /4. the repetitive nature of this signal eliminates quantization noise and distortion spurs as a factor in the measurement. although the curves blend together in figure 47, the different conditions are given for clarity in table 11. figure 47 also contains a table detailing pll divider settings versus interpolation rate and maximum and minimum f data rates. note that the maximum f data rates of 160 msps are due to the maximum input data rate of the ad7773. however, maximum rates of less than 160 msps and all minimum f data rates are due to the maximum and minimum speeds of the internal pll vco. figure 48 shows typical performance of the pll lock signal (pin 8 or 53) when the pll is in the process of locking. table 10. pll optimization interpolation rate divider setting minimum f data maximum f data 1 1 32 160 1 2 16 160 1 4 8 112 1 8 4 56 2 1 24 160 2 2 12 112 2 4 6 56 2 8 3 28 4 1 24 100 4 2 12 56 4 4 6 28 4 8 3 14 8 1 24 50 8 2 12 28 8 4 6 14 8 8 3 7 table 11. required pll prescaler ratio vs. f data f data pll prescaler ratio 125 msps disabled 125 msps enabled div 1 100 msps enabled div 2 75 msps enabled div 2 50 msps enabled div 4 ?110 ?100 ?80 ?40 ?20 0 ?60 ?90 ?50 ?30 ?10 ?70 phase noise (dbfs) 02857-b-047 012345 frequency offset (mhz) figure 47. phase noise performance
ad9773 rev. b | page 29 of 60 02857-b-048 figure 48. pll_lock output signal (pin 8) in the process of locking (typical lock time) it is important to note that the resistor/capacitor needed for the pll loop filter is internal on the ad9773. this will suffice unless the input data rate is below 10 mhz, in which case an external series rc is required between the lpf and clkvdd pins. power dissipation the ad9773 has three voltage supplies: dvdd, avdd, and clkvdd. figure 49, figure 50, and figure 51 show the current required from each of these supplies when each is set to the 3.3 v nominal specified for the ad9773. power dissipation (p d ) can easily be extracted by multiplying the given curves by 3.3. as figure 49 shows, i dvdd is very dependent on the input data rate, the interpolation rate, and the activation of the internal digital modulator. i dvdd , however, is relatively insensitive to the modulation rate by itself. in figure 50, i av dd shows the same type of sensitivity to the data, the interpolation rate, and the modulator function but to a much lesser degree (<10%). in figure 51, i clkvdd varies over a wide range yet is responsible for only a small percentage of the overall ad9773 supply current requirements. 8 4 2 1 0 50 100 150 200 250 i dvdd (ma) 300 350 400 02857-b-049 f data (mhz) 50 0 100 150 200 8 , (mod. on) 4 , (mod. on) 2 , (mod. on) figure 49. i dvdd vs. f data vs. interpolation rate, pll disabled 8 , (mod. on) 8 4 2 1 72.0 72.5 73.0 73.5 74.0 74.5 i avdd (ma) 75.0 75.5 76.0 02857-b-050 f data (mhz) 50 0 100 150 200 4 , (mod. on) 2 , (mod. on) figure 50. i avdd vs. f data vs. interpolation rate, pll disabled 8 4 1 2 0 5 10 15 20 25 30 35 i clkvdd (ma) 02857-b-051 f data (mhz) 50 0 100 150 200 figure 51. i clkvdd vs. f data vs. interpolation rate, pll disabled sleep/power-down modes (control register 00h, bits 3 and 4) the ad9773 provides two methods for programmable reduction in power savings. the sleep mode, when activated, turns off the dac output currents but the rest of the chip remains functioning. when coming out of sleep mode, the ad9773 will immediately return to full operation. power-down mode, on the other hand, turns off all analog and digital circuitry in the ad9773 except fo r the spi port. when returning from power-down mode, enough clock cycles must be allowed to flush the digital filters of random data acquired during the power-down cycle. two-port data input mode the digital data input ports can be configured as two independent ports or as a single (one-port mode) port. in the two-port mode, data at the two input ports is latched into the ad9773 on every rising edge of the data rate clock (dataclk). also, in the two-port mode, the ad9773 can be programmed to generate an externally available dataclk for the purpose of data synchronization. this data rate clock can be
ad9773 rev. b | page 30 of 60 programmed to be available at either pin 8 (dataclk/pll_lock) or pin 53 (spi_sdo). because pin 8 can also function as a pll lock indicator when the pll is enabled, there are several options for configuring pins 8 and 53. the following describes the options. pll off (register 4, bit 7 = 0) register 3, bit 7 = 0; dataclk out of pin 8. register 3, bit 7 = 1; dataclk out of pin 53. pll on (register 4, bit 7 = 1) register 3, bit 7 = 0, register 1, bit 0 = 0; pll lock indicator out of pin 8. register 3, bit 7 = 1, register 1, bit 0 = 0; pll lock indicator out of pin 53. register 3, bit 7 = 0, register 1, bit 0 = 1; dataclk out of pin 8. register 3, bit 7 = 1, register 1, bit 0 = 1; dataclk out of pin 53. in one-port mode, p2b14 and p2b15 from input data port two are redefined as iqsel and oneportclk, respectively. the input data in one-port mode is steered to one of the two internal data channels based on the logic level of iqsel. a clock signal, oneportclk, is generated by the ad9773 in this mode for the purpose of data synchronization. oneportclk runs at the input interleaved data rate, which is 2 the data rate at the internal input to either channel. test configurations showing the various clocks that are required and generated by the ad9773 with the pll enabled/disabled and in the one-port/two-port modes are given in figure 101 to figure 104. jumper positions needed to operate the ad9773 evaluation board in these modes are given as well. one-/two-port input modes the digital data input ports can be configured as two independent ports or as a single (one-port mode) port. in two- port mode, the ad9773 can be programmed to generate an externally available data rate clock (dataclk) for the purpose of data synchronization. data at the two input ports can be latched into the ad9773 on every rising clock edge of dataclk. in one-port mode, p2b10 and p2b11 from input data port 2 are redefined as iqsel and oneportclk, respectively. the input data in one-port mode is steered to one of the two internal data channels based on the logic level of iqsel. a clock signal, oneportclk, is generated by the ad9773 in this mode for the purpose of external data synchronization. oneportclk runs at the input interleaved data rate which is 2 the data rate at the internal input to either channel. test configurations showing the various clocks required and produced by the ad9773 in the pll and one-/two-port modes are given in figure 101 to figure 104. jumper positions needed to operate the ad9773 evaluation board in these modes are given as well. pll enabled, two-port mode (control register 02h, bits 6 to 0 and 04h, bits 7 to 1) with the phase-locked loop (pll) enabled and the ad9773 in two-port mode, the speed of clkin is inherently that of the input data rate . in two-port mode, pin 8 (dataclk/pll_ lock) can be programmed (control register 01h, bit 0) to function as either a lock indicator for the internal pll or as a clock running at the input data rate. when pin 8 is used as a clock output (dataclk), its frequency is equal to that of clkin. data at the input ports is latched into the ad9773 on the rising edge of the clkin. figure 52 shows the delay, t od , inherent between the rising edge of clkin and the rising edge of dataclk, as well as the setup and hold requirements for the data at ports 1 and 2. the setup and hold times given in figure 52 are the input data transitions with respect to clkin. note that in two-port mode (pll enabled or disabled), the data rate at the interpolation filter inputs is the same as the input data rate at ports 1 and 2. the dac output sample rate in two-port mode is equal to the clock input rate multiplied by the interpolation rate. if zero stuffing is used, another factor of 2 must be included to calculate the dac sample rate. dataclk inversion (control register 02h, bit 4) by programming this bit, the dataclk signal shown in figure 52 can be inverted. with inversion enabled, t od will refer to the time between the rising edge of clkin and the falling edge of dataclk. no other effect on timing will occur. t od t s t s = 0.0ns (max) t h = 2.5ns (max) t h clkin dataclk data at port s 1 and 2 02857-b-052 figure 52. timing requirements in two-port input mode with pll enabled
ad9773 rev. b | page 31 of 60 dataclk driver strength (control register 02h, bit 5) the dataclk output driver strength is capable of driving >10 ma into a 330 ? load while providing a rise time of 3 ns. figure 53 shows dataclk driving a 330 ? resistive load at a frequency of 50 mhz. by enabling the drive strength option (control register 02h, bit 5), the amplitude of dataclk under these conditions will be increased by approximately 200 mv. ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 amplitude (v) 02857-b-053 01020304050 time (ns) delta approx. 2.8ns figure 53. dataclk driver capability into 330 ? at 50 mhz pll enabled, one-port mode (control register 02h, bits 6 to1 and 04h, bits 7 to 1) in one-port mode, the i and q channels receive their data from an interleaved stream at digital input port 1. the function of pin 32 is defined as an output (oneportclk) that generates a clock at the interleaved data rate, which is 2 the internal input data rate of the i and q channels. the frequency of clkin is equal to the internal input data rate of the i and q channels. the selection of the data for the i or q channel is determined by the state of the logic level at pin 31 (iqsel when the ad9773 is in one-port mode) on the rising edge of oneportclk. under these conditions, iqsel = 0 will latch the data into the i channel on the clock rising edge, while iqsel = 1 will latch the data into the q channel. it is possible to invert the i and q selection by setting control register 02h, bit 1 to the invert state (logic 1). figure 54 illustrates the timing requirements for the data inputs as well as the iqsel input. note that the 1 interpolation rate is not available in the one-port mode. the dac output sample rate in one port mode is equal to clkin multiplied by the interpolation rate. if zero stuffing is used, another factor of two must be included to calculate the dac sample rate. oneportclk inversion (control register 02h, bit 2) by programming this bit, the oneportclk signal shown in figure 54 can be inverted. with inversion enabled, t od refers to the delay between the rising edge of the external clock and the falling edge of oneportclk. the setup and hold times, t s and t h , will be with respect to the falling edge of oneportclk. there is no other effect on timing. oneportclk driver strength the drive capability of oneportclk is identical to that of dataclk in the two-port mode. refer to figure 53 for performance under load conditions. 02857-b-054 t od t s t iqs t iqh t od = 4.0ns (min) to 5.5ns (max) t s = 3.0ns (max) t h = ?0.5ns (max) t iqs = 3.5ns (max) t iqh = ?1.5ns (max) t h clkin oneportclk iqsel i and q interleaved input data at port 1 figure 54. timing requirements in one-port input mode with the pll enabled iq pairing (control register 02h, bit 0) in one-port mode, the interleaved data is latched into the ad9773 internal i and q channels in pairs. the order of how the pairs are latched internally is defined by this control register. the following is an example of the effect this has on incoming interleaved data. given the following interleaved data stream, where the data indicates the value with respect to full scale: i q i q i q i q i q 0.5 0.5 1 1 0.5 0.5 0 0 0.5 0.5 with the control register set to 0 (i first), the data will appear at the internal channel inputs in the following order in time: i channel 0.5 1 0.5 0 0.5 q channel 0.5 1 0.5 0 0.5
ad9773 rev. b | page 32 of 60 with the control register set to 1 (q first), the data will appear at the internal channel inputs in the following order in time: i channel 0.5 1 0.5 0 0.5 x q channel y 0.5 1 0.5 0 0.5 the values x and y represent the next i value and the previous q value in the series. pll disabled, two-port mode with the pll disabled, a clock at the dac output rate must be applied to clkin. internal clock dividers in the ad9773 synthesize the dataclk signal at pin 8, which runs at the input data rate and can be used to synchronize the input data. data is latched into input ports 1 and 2 of the ad9773 on the rising edge of dataclk. dataclk speed is defined as the speed of clkin divided by the interpolation rate. with zero stuffing enabled, this division increases by a factor of two. figure 55 illustrates the delay between the rising edge of clkin and the rising edge of dataclk, as well as t s and t h in this mode. the programmable modes dataclk inversion and dataclk driver strength described in the previous section (pll enabled, two-port mode) have identical functionality with the pll disabled. the data rate clock created by dividing down the dac clock in this mode can be programmed (via register 03h, bit 7) to be output from the spi_sdo pin, rather than the dataclk pin. in some applications, this may improve complex image rejection. t od will increase by 1.6 ns when spi_sdo is used as data rate clock out. 02857-b-055 t od t s t h t od = 6.5ns (min) to 8.0ns (max) t s = 5.0ns (max) t h = ?3.2ns (max) clkin dataclk data at port s 1 and 2 figure 55. timing requirements in two-port input mode with pll disabled pll disabled, one-port mode in one-port mode, data is received into the ad9773 as an interleaved stream on port 1. a clock signal (oneportclk), running at the interleaved data rate, which is 2 the input data rate of the internal i and q channels, is available for data synchronization at pin 32. with pll disabled, a clock at the dac output rate must be applied to clkin. internal dividers synthesize the oneportclk signal at pin 32. the selection of the data for the i or q channel is determined by the state of the logic level applied to pin 31 (iqsel when the ad9773 is in one-port mode) on the rising edge of oneportclk. under these conditions, iqsel = 0 will latch the data into the i channel on the clock rising edge, while iqsel = 1 will latch the data into the q channel. it is possible to invert the i and q selection by setting control register 02h, bit 1 to the invert state (logic 1). figure 56 illustrates the timing requirements for the data inputs as well as the iqsel input. note that the 1 interpolation rate is not available in the one-port mode. one-port mode is very useful when interfacing with devices such as the analog devices ad6622 or ad6623 transmit signal processors, in which two digital data channels have been interleaved (multiplexed). the programmable modes oneportclk inversion, oneportclk driver strength and iq pairing described in the previous section (pll enabled, one-port mode) have identical functionality with the pll disabled. 02857-b-056 t od t s t iqs t iqh t h t od = 4.0ns (min) to 5.5ns (max) t s = 3.0ns (max) t h = ?1.0ns (max) t iqs = 3.5ns (max) t iqh = ?1.5ns (max) clkin iqsel oneportclk i and q interleaved input data at port 1 figure 56. timing requirements in one-port input mode with dll disabled digital filter modes the i and q data paths of the ad9773 have their own independent half-band fir filters. each data path consists of three fir filters, providing up to 8 interpolation for each channel. the rate of interpolation is determined by the state of control register 01h, bits 7 and 6. figure 2 to figure 4 show the response of the digital filters when the ad9773 is set to 2, 4, and 8 modes. the frequency axes of these graphs have been
ad9773 rev. b | page 33 of 60 normalized to the input data rate of the dac. as the graphs show, the digital filters can provide greater than 75 db of out-of-band rejection. an online tool is available for quick and easy analysis of the ad9773 interpolation filters in the various modes. the link can be accessed at www.analog.com/analog_root/static/ techsupport/designtools/interactivetools/dac/ ad9777image.html . amplitude modulation given two sine waves at the same frequency, but with a 90 phase difference, a point of view in time can be taken such that the waveform that leads in phase is cosinusoidal and the waveform that lags is sinusoidal. analysis of complex variables states that the cosine waveform can be defined as having real positive and negative frequency components, while the sine waveform consists of imaginary positive and negative frequency images. this is shown graphically in the frequency domain in figure 57. 02857-b-057 e ?j t /2j e ?j t /2j e ?j t /2 e ?j t /2 dc dc cosine sine figure 57. real and imaginary components of sinusoidal and cosinusoidal waveforms amplitude modulating a baseband signal with a sine or a cosine convolves the baseband signal with the modulating carrier in the frequency domain. amplitude scaling of the modulated signal reduces the positive and negative frequency images by a factor of 2. this scaling will be very important in the discussion of the various modulation modes. the phase relationship of the modulated signals is dependent on whether the modulating carrier is sinusoidal or cosinusoidal, again with respect to the reference point of the viewer. examples of sine and cosine modulation are given in figure 58. 02857-b-058 dc sinusoidal modulation cosinusoidal modulation dc ae ?j t /2j ae ?j t /2j ae ?j t /2 ae ?j t /2 figure 58. baseband signal, amplitude modulated with sine and cosine carriers
ad9773 rev. b | page 34 of 60 modulation, no interpolation with control register 01h, bits 7 and 6 set to 00, the interpolation function on the ad9773 is disabled. figure 59 to figure 62 show the dac output spectral characteristics of the ad9773 in the various modulation modes, all with the interpolation filters disabled. the modulation frequency is determined by the state of control register 01h, bits 5 and 4. the tall rectangles represent the digital domain spectrum of a baseband signal of narrow bandwidth. by comparing the digital domain spectrum to the dac sin(x)/x roll-off, an estimate can be made for the characteristics required for the dac reconstruction filter. note also, per the previous discussion on amplitude modulation, that the spectral components (where modulation is set to f s /4 or f s /8) are scaled by a factor of 2. in the situation where the modulation is f s /2, the modulated spectral components add constructively, and there is no scaling effect. the effects of the digital modulation on the dac output spectrum, interpolation disabled ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-059 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) figure 59. no interpolation, modulation disabled ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-060 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) figure 60. no interpolation, modulation = f dac /2 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-061 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) figure 61. no interpolation, modulation = f dac /4 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-062 0 0.2 0.4 0.6 0.8 1.0 f out ( f data ) figure 62. no interpolation, modulation = f dac /8
ad9773 rev. b | page 35 of 60 modulation, interpolation = 2 with control register 01h, bits 7 and 6 set to 01, the interpolation rate of the ad9773 is 2. modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (+1, ?1). figure 63 to figure 66 represent the spectral response of the ad9773 dac output with 2 interpolation in the various modulation modes to a narrow band baseband signal (again, the tall rectangles in the graphic). the advantage of interpolation becomes clear in figure 63 to figure 66, where it can be seen that the images that would normally appear in the spectrum around the input data rate frequency are suppressed by >70 db. another significant point is that the interpolation filtering is done previous to the digital modulator. for this reason, as figure 63 to figure 66 show, the pass band of the interpolation filters can be frequency shifted, giving the equivalent of a high-pass digital filter. note that when using the f s /4 modulation mode, there is no true stop band as the band edges coin cide with each other. in the f s /8 modulation mode, amplitude scaling occurs over only a portion of the digital filter pass band due to constructive addition over just that section of the band. the effects of the digital modulation on the dac output spectrum, interpolation = 2x ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-063 f out ( f data ) 0.5 0 1.0 1.5 2.0 figure 63. 2x interpolation, modulation = disabled ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-064 f out ( f data ) 0.5 0 1.0 1.5 2.0 figure 64. 2x interpolation, modulation = f dac /2 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-065 f out ( f data ) 0.5 0 1.0 1.5 2.0 figure 65. 2x interpolation, modulation = f dac /4 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-066 f out ( f data ) 0.5 0 1.0 1.5 2.0 figure 66. 2x interpolation, modulation = f dac /8
ad9773 rev. b | page 36 of 60 modulation, interpolation = 4 with control register 01h, bits 7 and 6 set to 10, the interpolation rate of the ad9773 is 4. modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +1, 0, ?1). figure 67 to figure 70 represent the spectral response of the ad9773 dac output with 4 interpolation in the various modulation modes to a narrow band baseband signal. the effects of the digital modulation on the dac output spectrum interpolation = 4x ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857 b 067 f out ( f data ) 1 0234 figure 67. 4x interpolation, modulation disabled ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857 b 068 f out ( f data ) 1 0234 figure 68. 4x interpolation, modulation = f dac /2 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857 b 069 f out ( f data ) 1 0234 figure 69. 4x interpolation, modulation = f dac /4 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857 b 070 f out ( f data ) 1 0234 figure 70. 4x interpolation, modulation = f dac /8
ad9773 rev. b | page 37 of 60 modulation, interpolation = 8 with control register 01h, bits 7 and 6 set to 11, the interpolation rate of the ad9773 is 8. modulation is achieved by multiplying successive samples at the interpolation filter output by the sequence (0, +0.707, +1, +0.707, 0, ?0.707, ?1, +0.707). figure 71 to figure 74 represent the spectral response of the ad9773 dac output with 8 interpolation in the various modulation modes to a narrow band baseband signal. looking at figure 63 to figure 75, the user can see how higher interpolation rates reduce the complexity of the reconstruction filter needed at the dac output. it also becomes apparent that the ability to modulate by f s /2, f s /4, or f s /8 adds a degree of flexibility in frequency planning. the effects of the digital modulation on the dac output spectrum, interpolation = 8x ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-071 f out ( f data ) 1 0234 figure 71. 8x interpolation, modulation disabled ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 02857-b-072 f out ( f data ) 1 0234 figure 72. 8x interpolation, modulation = f dac /2 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 4 3 12 05678 f out ( f data ) 02857-b-073 figure 73. 8x interpolation, modulation = f dac /4 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 4 3 12 05678 f out ( f data ) 02857-b-074 figure 74. 8x interpolation, modulation = f dac /8
ad9773 rev. b | page 38 of 60 zero stuffing (control register 01h, bit 3) as shown in figure 75, a 0 or null in the output frequency response of the dac (after interpolation, modulation, and dac reconstruction) occurs at the final dac sample rate (f dac ). this is due to the inherent sin(x)/x roll-off response in the digital- to-analog conversion. in applications where the desired frequency content is below f dac /2, this may not be a problem. note that at f dac /2 the loss due to sin(x)/x is 4 db. in direct rf applications, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced amplitude of the desired signal. consider an application where the digital data into the ad9773 represents a baseband signal around f dac /4 with a pass band of f dac /10. the reconstructed signal out of the ad9773 would experience only a 0.75 db amplitude variation over its pass band. however, the image of the same signal occurring at 3 f dac /4 will suffer from a pass-band flatness variation of 3.93 db. this image may be the desired signal in an if application using one of the various modulation modes in the ad9773. this roll- off of image frequencies can be seen in figure 59 to figure 74, where the effect of the interpolation and modulation rate is apparent as well. ?50 ?40 ?30 ?20 ?10 0 10 sin (x) /x roll-off (dbfs) 02857-b-075 f out , normalized to f data with zero stuffing disabled (hz) 0.5 0 1.0 1.5 2.0 zero stuffing enabled zero stuffing disabled figure 75. effect of zero stuffing on dacs sin(x)/x response to improve upon the pass-band flatness of the desired image, the zero stuffing mode can be enabled by setting the control register bit to logic 1. this option increases the ratio of f dac /f data by a factor of 2 by doubling the dac sample rate and inserting a midscale sample (i.e., 1000 0000 0000 0000) after every data sample originating from the interpolation filter. this is important as it will affect the pll divider ratio needed to keep the vco within its optimum speed range. note that the zero stuffing takes place in the digital signal chain at the output of the digital modulator, before the dac. the net effect is to increase the dac output sample rate by a factor of 2 with the 0 in the sin(x)/x dac transfer function occurring at twice the original frequency. a 6 db loss in amplitude at low frequencies is also evident, as can be seen in figure 76. it is important to realize that the zero stuffing option by itself does not change the location of the images but rather their amplitude, pass-band flatness, and relative weighting. for instance, in the previous example, the pass-band amplitude flatness of the image at 3 f data /4 is now improved to 0.59 db while the signal level has increased slightly from ?10.5 dbfs to ?8.1 dbfs. interpolating (complex mix mode) (control register 01h, bit 2) in the complex mix mode, the two digital modulators on the ad9773 are coupled to provide a complex modulation function. in conjunction with an external quadrature modulator, this complex modulation can be used to realize a transmit image rejection architecture. the complex modulation function can be programmed for e +jt or e ?jt to give upper or lower image rejection. as in the real modulation mode, the modulation frequency can be programmed via the spi port for f dac /2, f dac /4, and f dac /8, where f dac represents the dac output rate. operations on complex signals truly complex signals cannot be realized outside of a computer simulation. however, two data channels, both consisting of real data, can be defined as the real and imaginary components of a complex signal. i (real) and q (imaginary) data paths are often defined this way. by using the architecture defined in figure 76, a system can be realized that operates on complex signals, giving a complex (real and imaginary) output. if a complex modulation function (e +jt ) is desired, the real and imaginary components of the system correspond to the real and imaginary components of e +jt or cost and sint. as figure 77 shows, the complex modulation function can be realized by applying these components to the structure of the complex system defined in figure 76. 02857-b-076 a(t) = (c + jd) b(t) c(t) b(t) + d b(t) b(t) a(t) + c b(t) input output input output complex filter imaginary figure 76. realization of a complex system
ad9773 rev. b | page 39 of 60 02857-b-077 input (real) output (real) output (imaginary) input (imaginary) 90 e ?j t = cos t + jsin t figure 77. implementation of a complex modulator complex modulation and image rejection of baseband signals in traditional transmit applications, a two-step upconversion is done in which a baseband signal is modulated by one carrier to an if (intermediate frequency) and then modulated a second time to the transmit frequency. although this approach has several benefits, a major drawback is that two images are created near the transmit frequency. only one image is needed, the other being an exact duplicate. unless the unwanted image is filtered, typically with analog components, transmit power is wasted and the usable bandwidth available in the system is reduced. a more efficient method of suppressing the unwanted image can be achieved by using a complex modulator followed by a quadrature modulator. figure 78 is a block diagram of a quadrature modulator. note that it is in fact the real output half of a complex modulator. the complete upconversion can actually be referred to as two complex upconversion stages, the real output of which becomes the transmitted signal. 02857-b-078 input (real) output input (imaginary ) 90 cos t sin t figure 78. quadrature modulator the entire upconversion from baseband to transmit frequency is represented graphically in figure 79. the resulting spectrum shown in figure 79 represents the complex data consisting of the baseband real and imaginary channels, now modulated onto orthogonal (cosine and negative sine) carriers at the transmit frequency. it is important to remember that in this application (two baseband data channels) the image rejection is not dependent on the data at either of the ad9773 input channels. in fact, image rejection will still occur with either one or both of the ad9773 input channels active. note that by changing the sign of the sinusoidal multiplying term in the complex modulator, the upper sideband image could have been suppressed while passing the lower one. this is easily done in the ad9773 by selecting the e +jt bit (register 01h, bit 1). in purely complex terms, figure 79 represents the two-stage upconversion from complex baseband to carrier.
ad9773 rev. b | page 40 of 60 02857-b-079 real channel (out) imaginary channel (out) a/2 ?b/2j b/2j ?a/2j a/2j ?f c 1 f c f c ?f c ?f c ?f c f c ?f c a/2 b/2 b/2 complex modulator to quadrature modulator real channel (in) imaginary channel (in) a dc b dc a/4 + b/4j a/4 ? b/4j a/4 + b/4j a/4 ? b/4j ?a/4 ? b/4j a/2 + b/2j a/2 ? b/2j a/4 ? b/4j a/4 + b/4j ?a/4 + b/4j ?f q ? f c ?f q + f c ?f q 2 ?f q f q ?f q f q f q ? f c f q + f c f q quadrature modulator out real imaginary rejected images notes 1 f c = complex modulation frequency 2 f q = quadrature modulation frequency figure 79. two-stage upconversion and resulting image rejection
ad9773 rev. b | page 41 of 60 02857-b-080 complex baseband signal output = real = real frequency 1 1/2 1/2 ? 1? 2dc e j( 1 + 2)t 1 + 2 figure 80. two-stage complex upconversion image rejection and sideband suppression of modulated carriers as shown in figure 79, image rejection can be achieved by applying baseband data to the ad9773 and following the ad9773 with a quadrature modulator. to process multiple carriers while still maintaining image reject capability, each carrier must be complex modulated. as figure 80 shows, single or multiple complex modulators can be used to synthesize complex carriers. these complex carriers are then summed and applied to the real and imaginary inputs of the ad9773. a system in which multiple baseband signals are complex modulated and then applied to the ad9773 real and imaginary inputs followed by a quadrature modulator is shown in figure 82, which also describes the transfer function of this system and the spectral output. note the similarity of the transfer functions given in figure 82 and figure 80. figure 82 adds an additional complex modulator stage for the purpose of summing multiple carriers at the ad9773 inputs. also, as in figure 79, the image rejection is not dependent on the real or imaginary baseband data on any channel. image rejection on a channel will occur if either the real or imaginary data, or both, is present on the baseband channel. it is important to remember that the magnitude of a complex signal can be 1.414 the magnitude of its real or imaginary components. due to this 3 db increase in signal amplitude, the real and imaginary inputs to the ad9773 must be kept at least 3 db below full scale when operating with the complex modulator. overranging in the complex modulator will result in severe distortion at the dac output. 02857-b-081 baseband channel 1 real input baseband channel 2 real input baseband channel n real input imaginary input imaginary input imaginary input complex modulator 1 complex modulator 2 complex modulator n r(1) r(1) r(2) r(2) r(n) r(n) multicarrier real output = r(1) + r(2) + . . .r(n) (to real input of ad9773) multicarrier imaginary output = i(1) + i(2) + . . .i(n) (to imaginary input of ad9773) r(n) = real output of n i(n) = imaginary output of n figure 81. synthesis of multicarrier complex signal 02857-b-082 multiple baseband channels multiple complex modulators frequency = 1 , 2 ... n real imaginary real output = real imaginary real real imaginary ad9773 complex modulator frequency = c quadrature modulator frequency = q complex baseband signal rejected images dc e j( n + c + q )t ? 1 ? c ? q 1 + c + q figure 82. image rejection with multicarrier signals
ad9773 rev. b | page 42 of 60 the complex carrier synthesized in the ad9773 digital modulator is accomplished by creating two real digital carriers in quadrature. carriers in quadrature cannot be created with the modulator running at f dac /2. as a result, complex modulation only functions with modulation rates of f dac /4 and f dac /8. regions a and b of figure 83 to figure 88 are the result of the complex signal described previously, when complex modulated in the ad9773 by +e jt . regions c and d are the result of the complex signal described previously, again with positive frequency components only, modulated in the ad9773 by ?e jt . the analog quadrature modulator after the ad9773 inherently modulates by +e jt . region a region a is a direct result of the upconversion of the complex signal near baseband. if viewed as a complex signal, only the images in region a will remain. the complex signal a, consisting of positive frequency components only in the digital domain, has images in the positive odd nyquist zones (1, 3, 5...), as well as images in the negative even nyquist zones. the appearance and rejection of images in every other nyquist zone will become more apparent at the output of the quadrature modulator. the a images will appear on the real and the imaginary outputs of the ad9773, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator lo and the horizontal scale now represents the frequency offset from this lo. region b region b is the image (complex conjugate) of region a. if a spectrum analyzer is used to view the real or imaginary dac outputs of the ad9773, region b will appear in the spectrum. however, on the output of the quadrature modulator, region b will be rejected. region c region c is most accurately described as a down conversion, as the modulating carrier is ?e jt . if viewed as a complex signal, only the images in region c will remain. this image will appear on the real and imaginary outputs of the ad9773, as well as on the output of the quadrature modulator, where the center of the spectral plot will now represent the quadrature modulator lo and the horizontal scale will represent the frequency offset from this lo. region d region d is the image (complex conjugate) of region c. if a spectrum analyzer is used to view the real or imaginary dac outputs of the ad9773, region d will appear in the spectrum. however, on the output of the quadrature modulator, region d will be rejected. figure 89 to figure 96 show the measured response of the ad9773 and ad8345 given the complex input signal to the ad9773 in figure 89. the data in these graphs was taken with a data rate of 12.5 msps at the ad9773 inputs. the interpolation rate of 4 or 8 gives a dac output data rate of 50 msps or 100 msps. as a result, the high end of the dac output spectrum in these graphs is the first null point for the sin(x)/x roll-off, and the asymmetry of the dac output images is representative of the sin(x)/x roll-off over the spectrum. the internal pll was enabled for these results. in addition, a 35 mhz third-order low-pass filter was used at the ad9773/ad8345 interface to suppress dac images. an important point can be made by looking at figure 91 and figure 93. figure 91 represents a group of positive frequencies modulated by complex +f dac /4, while figure 93 represents a group of negative frequencies modulated by complex ?f dac /4. when looking at the real or imaginary outputs of the ad9773, as shown in figure 91 and figure 93, the results look identical. however, the spectrum analyzer cannot show the phase relationship of these signals. the difference in phase between the two signals becomes apparent when they are applied to the ad8345 quadrature modulator, with the results shown in figure 92 and figure 94.
ad9773 rev. b | page 43 of 60 ?100 ?80 ?60 ?40 ?20 0 0 ?0.5 ?1.5 ?1.0 ?2.0 0.5 1.0 1.5 2.0 (lo) f out ( f data ) 02857-b-083 dabcdabc figure 83. 2x interpolation, complex f dac /4 modulation ?100 ?80 ?60 ?40 ?20 0 0 ?1.0 ?3.0 ?2.0 ?4.0 1.0 2.0 3.0 4.0 (lo) f out ( f data ) 02857-b-084 d a bc da bc figure 84. 4x interpolation, complex f dac /4 modulation ?100 ?80 ?60 ?40 ?20 0 0 ?2.0 ?6.0 ?4.0 ?8.0 2.0 4.0 6.0 8.0 (lo) f out ( f data ) 02857-b-085 da b c da b c figure 85. 8x interpolation, complex f dac /4 modulation ? 100 ?80 ?60 ?40 ?20 0 0 ?0.5 ?1.5 ?1.0 ?2.0 0.5 1.0 1.5 2.0 (lo) f out ( f data ) 02857-b-086 da b cd a bc figure 86. 2x interpolation, complex f dac /8 modulation ?100 ?80 ?60 ?40 ?20 0 0 ?1.0 ?3.0 ?2.0 ?4.0 1.0 2.0 3.0 4.0 (lo) f out ( f data ) 02857-b-087 da b cd a b c figure 87. 4x interpolation, complex f dac /8 modulation ?100 ?80 ?60 ?40 ?20 0 0 ?2.0 ?6.0 ?4.0 ?8.0 2.0 4.0 6.0 8.0 (lo) f out ( f data ) 02857-b-088 da da bc bc figure 88. 8x interpolation, complex f dac /8 modulation
ad9773 rev. b | page 44 of 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-089 frequency (mhz) 10 0203040 figure 89. ad9773 real dac output of complex input signal near baseband (positive frequencies only), interpolation = 4x, no modulation in ad9773 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 790 780 760 770 750 800 810 820 830 frequency (mhz) 02857-b-090 figure 90. ad9773 complex output from figure 89, now quadrature modulated by ad8345 (lo = 800 mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-091 frequency (mhz) 10 0203040 figure 91. ad9773 real dac output of complex input signal near baseband (positive frequencies only), interpolation = 4x, complex modulation in ad9773 = +f dac /4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 790 780 760 770 750 800 810 820 830 frequency (mhz) 02857-b-092 figure 92. ad9773 complex output from figure 91, now quadrature modulated by ad8345 (lo = 800 mhz)
ad9773 rev. b | page 45 of 60 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-093 frequency (mhz) 10 0203040 figure 93. ad9773 real dac output of complex input signal near baseband (negative frequencies only), interpolation = 4x, complex modulation in ad9773 = ?f dac /4 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 790 780 760 770 750 800 810 820 830 frequency (mhz) 02857-b-094 figure 94. ad9773 complex output from figure 93, now quadrature modulated by ad8345 (lo = 800 mhz) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 02857-b-095 frequency (mhz) 20 0406080 figure 95. ad9773 real dac output of complex input signal near baseband (positive frequencies only), interpolation = 8x, complex modulation in ad9773 = +f dac /8 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbm) 780 760 720 740 700 800 820 840 860 frequency (mhz) 02857-b-096 figure 96. ad9773 complex output from figure 95, now quadrature modulated by ad8345 (lo = 800 mhz)
ad9773 rev. b | page 46 of 60 applying the ad9773 output configurations the following sections illustrate typical output configurations for the ad9773. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requiring optimum dynamic performance, a differential output configuration is suggested. a simple differential output may be achieved by converting i outa and i outb to a voltage output by terminating them to agnd via equal value resistors. this type of configuration may be useful when driving a differential voltage input device such as a modulator. if a conversion to a single- ended signal is desired and the application allows for ac-coupling, an rf transformer may be useful, or if power gain is required, an op amp may be used. the transformer configuration provides optimum high frequency noise and distortion performance. the differential op amp configuration is suitable for applications requiring dc-coupling, signal gain, and/or level shifting within the bandwidth of the chosen op amp. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to a load resistor, r load , referred to agnd. this configuration is most suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter, thus converting i outa or i outb into a negative unipolar voltage. this configuration provides the best dac dc linearity as i outa or i outb are maintained at ground or virtual ground. unbuffered differ ential output, equivalent circuit in many applications, it may be necessary to understand the equivalent dac output circuit. this is especially useful when designing output filters or when driving inputs with finite input impedances. figure 97 illustrates the output of the ad9773 and the equivalent circuit. a typical application where this information may be useful is when designing an interface filter between the ad9773 and the analog devices ad8345 quadrature modulator. i outa i outb ad9773 r a v out + r b v out ? v out (differential) v source = i outfs (r a + r b ) p-p r a + r b 02857-b-097 figure 97. dac output equivalent circuit for the typical situation, where i outfs = 20 ma and r a and r b both equal 50 ?, the equivalent circuit values become v source = 2 v p-p r out = 100 ? note that the output impedance of the ad9773 dac itself is greater than 100 k? and typically has no effect on the impedance of the equivalent output circuit. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion, as shown in figure 98. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers pass band. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common- mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. transformers with different impedance ratios may also be used for impedance matching purposes. i outa i outb dac r load mini-circuits t1-1t 02857-b-098 figure 98. transformer-coupled output circuit the center tap on the primary side of the transformer must be connected to agnd to provide the necessary dc current path for both i outa and i outb . the complementary voltages appearing at i outa and i outb (i.e., v outa and v outb ) swing symmetrically around agnd and should be maintained within the specified output compliance range of the ad9773. a differential resistor, r diff , may be inserted in applications where the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformers impedance ratio and provides the proper source termination that results in a low vswr. note that approximately half the signal power will be dissipated across r diff .
ad9773 rev. b | page 47 of 60 differential coupling using an op amp an op amp can also be used to perform a differential-to-single- ended conversion, as shown in figure 99. this has the added benefit of providing signal gain as well. in figure 99, the ad9773 is configured with two equal load resistors, r load , of 25 ?. the differential voltage developed across i outa and i outb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across i outa and i outb , forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion performance by preventing the dacs fast slewing output from overloading the input of the op amp. i outa i outb dac 25 ? ad8021 500 ? c opt 225 ? 225 ? 500 ? r opt 225 ? avdd 25 ? 02857-b-099 figure 99. op amp-coupled output circuit the common-mode (and second-order distortion) rejection of this configuration is typically determined by the resistor matching. the op amp used must operate from a dual supply since its output is approximately 1.0 v. a high speed amplifier, such as the ad8021, capable of preserving the differential performance of the ad9773 while meeting other system level objectives (i.e., cost, power) is recommended. the op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. r opt is necessary only if level shifting is required on the op amp output. in figure 99, avdd, which is the positive analog supply for both the ad9773 and the op amp, is also used to level shift the differential output of the ad9773 to midsupply (i.e., avdd/2). interfacing the ad9773 with the ad8345 quadrature modulator the ad9773 architecture was defined to operate in a transmit signal chain using an image reject architecture. a quadrature modulator is also required in this application and should be designed to meet the output characteristics of the dac as much as possible. the ad8345 from analog devices meets many of the requirements for interfacing with the ad9773. as with any dac output interface, there are a number of issues that have to be resolved. among the major issues are the following. dac compliance voltage/input common-mode range the dynamic range of the ad9773 is optimal when the dac outputs swing between 1.0 v. the input common-mode range of the ad8345, at 0.7 v, allows optimum dynamic range to be achieved in both components. gain/offset adjust the matching of the dac output to the common-mode input of the ad8345 allows the two components to be dc-coupled, with no level shifting necessary. the combined voltage offset of the two parts can therefore be compensated for via the ad9773 programmable offset adjust. this allows excellent lo cancellation at the ad8345 output. the programmable gain adjust allows for optimal image rejection as well. the ad9773 evaluation board includes an ad8345 and recommended interface (figure 105 and figure 106). on the output of the ad9773, r9 and r10 convert the dac output current to a voltage. r16 may be used to do a slight common- mode shift if necessary. the (now voltage) signal is applied to a low-pass reconstruction filter to reject dac images. the components installed on the ad9773 provide a 35 mhz cutoff but may be changed to fit the application. a balun (mini- circuits adtl1-12) is used to cross the ground plane boundary to the ad8345. another balun (mini-circuits etc1-1-13) is used to couple the lo input of the ad8345. the interface requires a low ac impedance return path from the ad8345, so a single connection between the ad9773 and ad8345 ground planes is recommended. the performance of the ad9773 and ad8345 in an image reject transmitter, reconstructing three wcdma carriers, can be seen in figure 100. the lo of the ad8345 in this application is 800 mhz. image rejection (50 db) and lo feedthrough (?78 dbfs) have been optimized with the programmable features of the ad9773. the average output power of the digital waveform for this test was set to ?15 dbfs to account for the peak-to-average ratio of the wcdma signal. frequency (mhz) amplitude (dbm) ?80 762.5 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?90 ?100 782.5 802.5 822.5 842.5 02857-b-100 figure 100. ad9773/ad8345 synthesizing a three-carrier wcdma signal at an lo of 800 mhz
ad9773 rev. b | page 48 of 60 evaluation board the ad9773 evaluation board allows easy configuration of the various modes, programmable via the spi port. software is available for programming the spi port from win95?, win98?, or windows nt?/2000. the evaluation board also contains an ad8345 quadrature modulator and support circuitry that allows the user to optimally configure the ad9773 in an image reject transmit signal chain. figure 101 through figure 104 describe how to configure the evaluation board in the one- and two-port input modes with the pll enabled and disabled. refer to figure 105 through figure 114, the schematics, and the layout for the ad9773 evaluation board for the jumper locations described below. the ad9773 outputs can be configured for various applications by referring to the following instructions. dac single-ended outputs remove transformers t2 and t3. solder jumper link jp4 or jp28 to look at the dac1 outputs. solder jumper link jp29 or jp30 to look at the dac2 outputs. jumper 8 and jumpers 13 to 17 should remain unsoldered. jumpers jp35 to jp38 may be used to ground one of the dac outputs while the other is measured single ended. optimum single-ended distortion performance is typically achieved in this manner. the outputs are taken from s3 and s4. dac differential outputs transformers t2 and t3 should be in place. note that the lower band of operation for these transformers is 300 khz to 500 khz. jumpers 4, 8, 13 to 17, and 28 to 30 should remain unsoldered. the outputs are taken from s3 and s4. using the ad8345 remove transformers t2 and t3. jumpers jp4 and 28 to 30 should remain unsoldered. jumper s 13 to 16 should be soldered. the desired components for the low-pass interface filters l6, l7, c55, and c81 should be in place. the lo drive is connected to the ad8345 via j10 and the balun t4; and the ad8345 output is taken from j9.
ad9773 rev. b | page 49 of 60 signal generator clk+/clk? dataclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db11?db0 ad9773 dac2, db11?db0 40-pin ribbon cable jumper configuration for two port mode pll on jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02857-b-101 figure 101. 1 test configuration for ad9773 in two-port mode with pll enabled, signal generator frequency = input data rate, dac output data rate = signal generator frequency interpolation rate 2 signal generator clk+/clk? oneportclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db11?db0 ad9773 dac2, db11?db0 jumper configuration for one port mode pll on jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02857-b-102 figure 102. 1 test configuration for ad9773 in one-port mode with pll enabled, signal generator frequency = one-half interleaved input data rate, oneportclk = interleaved input data rate, dac output data rate = signal generator frequency interpolation rate 1 to use pecl driver (u8), solder jp41 and jp42 and remove transformer t1. 2 in two-port mode, if dataclk/pll_lock is programmed to output pin 8, jp25 and jp39 sh ould be soldered. if dataclk/pll_lock is programmed to output pin 53, jp46 and jp47 should be soldered. for more information, see the two-port data input mode section.
ad9773 rev. b | page 50 of 60 signal generator clk+/clk? dataclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db11?db0 ad9773 dac2, db11?db0 jumper configuration for two port mode pll off jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02857-b-103 40-pin ribbon cable figure 103. 1 test configuration for ad9773 in two-port mode with pll disabled, dac output data rate = signal generator frequency, dataclk = signal generator frequency/interpolation rate 2 signal generator clk+/clk? oneportclk lecroy pulse generator trig inp awg2021 or dg2020 input clock dac1, db11?db0 ad9773 dac2, db11?db0 jumper configuration for one port mode pll off jp1 ? jp2 ? jp3 ? jp5 ? jp6 ? jp12 ? jp24 ? jp25 ? jp26 ? jp27 ? jp31 ? jp32 ? jp33 ? soldered/in unsoldered/out 02857-b-104 figure 104. 1 test configuration for ad9773 in one-port mode with pll disabled, dac output data rate = signal generator frequency, oneportclk = interleaved input data rate = 2x signal generator frequency/interpolation rate 1 to use pecl driver (u8), solder jp41 and jp42 and remove transformer t1. 2 in two-port mode, if dataclk/pll_lock is programmed to output pin 8, jp25 and jp39 sh ould be soldered. if dataclk/pll_lock is programmed to output pin 53, jp46 and jp47 should be soldered. for more information, see the two-port data input mode section.
ad9773 rev. b | page 51 of 60 jp21 jp7 c54 dnp r28 0 ? r26 1k ? r35 51 ? r36 51 ? jp20 c79 dnp r32 51 ? r34 dnp c69 0.1 f c63 16v 22 f clkvdd_in j7 tp6 red tp7 blk c62 16v 22 f clkvdd l1 ferrite r33 51 ? c78 0.1 f jp18 vddm c72 10v 10 f c75 0.1 f o2n o2p o1n o1p jp19 vddm c74 100pf c35 100pf vddm c76 100pf c77 100pf r30 dnp j10 dgnd2; 3, 4, 5 j9 dgnd2; 3, 4, 5 j3 cgnd ad8345 u2 2 2 2 2 2 rc0603 rc0603 rc0603 rc0603 rc0603 rc0603 cc0603 rc0603 rc0603 lc1210 rc0603 cc0603 bcase cc0603 cc0603 cc0603 rc0603 g2 enbl vps1 g1a g1b loip vps2 g4a g4b qbbp vout g3 ibbp ibbn loin local osc input modulated output power input filters lc0805 l6 dnp lc0805 l7 dnp l4 dnp l5 dnp jp11 cc0805 dcase dcase cc0805 t6 6 adtl1-12 p s 4 31 2 2 c80 dnp cc0603 r37 dnp c73 dnp cc0805 cc0805 lc0805 lc0805 2 cc0603 qbbn r23 0 ? cc0805 c81 dnp c55 dnp 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 t4 5 etc1-1-13 sp 4 3 1 t5 3 adtl1-12 s p 1 64 cc0603 jp43 jp45 2 jp44 c68 0.1 f c64 16v 22 f avdd_in j6 tp4 red tp5 blk c61 16v 22 f avdd j4 agnd lc1210 jp10 jp9 cc0805 dcase dcase l2 ferrite c67 0.1 f c65 16v 22 f dvdd_in j5 tp2 red tp3 blk c66 16v 22 f dvdd l3 ferrite j8 dgnd lc1210 cc0805 dcase dcase c32 0.1 f c28 16v 22 f vddmin w12 l8 ferrite w11 dgnd2 lc1210 cc0805 dcase 02857-b-105 c + + + + + + + + figure 105. ad8345 circuitry on ad9773 evaluation board
ad9773 rev. b | page 52 of 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 dvdd c c c r2 1k ? r3 1k ? clkvdd dvdd rc0603 rc0603 bcase bcase cc0603 cc0603 cc0603 cc0603 rc0603 tp15 wht t1 t1-1t tp14 wht r1 200 ? r40 5k ? r5 49.9 ? r39 1k ? c13 0.1 f c1 10 f 6.3v c10 10 f 6.3v c26 0.001 f c12 0.1 f c11 0.1 f c42 0.1 f cc0603 cc0805 c27 1pf c36 0.1 f cc0805 c37 0.1 f cc0805 c38 0.1 f cc0805 c39 0.1 f cc0805 c40 0.1 f cc0805 c41 0.1 f + + c jp22 jp23 jp33 jp1 clkp clkn r38 10k ? jp2 s1 s2 s6 12 11 13 iq iq s5 u4 adclk dvdd clkin aclkx cgnd; 3, 4, 5 dgnd; 3, 4, 5 dataclk jp39 jp24 jp5 bd15 bd14 opclk_3 opclk 74vcx86 opclk dgnd; 3, 4, 5 dgnd; 7 dvdd; 14 agnd; 3, 4, 5 jp27 jp40 jp34 jp32 jp26 jp31 jp3 cx2 74vcx86 12 13 11 u3 dvdd; 14 dvdd dgnd; 7 cx1 jp25 jp12 cx3 6 5 4 1 2 3 rc0603 cc0603 bcase c9 10 f 6.3v c25 0.001 f + dvdd cc0603 bcase c8 10 f 6.3v c24 0.001 f + dvdd cc0603 bcase c7 10 f 6.3v c23 0.001 f + dvdd cc0603 cc0605 cc0805 rc0603 c29 0.1 f c45 0.01 f ad15 vddc1 vdda6 vssa10 vdda5 vssa9 vdda4 vssa8 vssa7 iout1p iout1n vssa6 vssa5 iout2p iout2n vssa4 vssa3 vdda3 vssa2 vssa1 vssd6 vddd6 p2d0 p2d1 p2d2 p2d3 p2d4 p2d5 p2d6 p2d7 vssd5 vddd5 vdda2 vdda1 fsadj1 fsadj2 refout reset sp-csb sp-clk sp-sdi sp-sdo lf vddc2 vssc1 clkp clkn vssc2 dclk-plll vssd1 vddd1 p1d15 p1d14 p1d13 p1d12 p1d11 p1d10 vssd2 vddd2 p1d9 p1d8 p1d7 p1d6 p1d5 p1d4 vssd3 vddd3 p1d3 p1d2 p1d1 p1d0 p2d15-iqsel p2d14-opclk p2d13 p2d12 p2d11 p2d10 p2d9 p2d8 vssd4 vddd4 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 bd13 bd12 bd11 bd10 bd09 bd08 ad9773+tsp u1 c20 0.1 f cc0603 c19 0.1 f cc0603 cc0603 cc0603 cc0603 cc0603 rc1206 c14 0.1 f bcase cc0603 c2 10 f 6.3v + c18 0.1 f cc0603 bcase c17 0.1 f c16 0.1 f cc0603 c21 0.001 f cc0603 cc0603 c15 0.1 f bcase cc0805 c3 10 f 6.3v c4 10 f 6.3v r7 2k ? 0.01% r8 1k ? 0.01% + + bcase c5 10 f 6.3v + c58 dnp c58 dnp c57 dnp c59 dnp r6 1k ? avdd avdd dvdd cc0603 c22 0.001 f bcase c6 10 f 6.3v + dvdd tp11 wht tp10 wht tp9 wht tp8 wht spcsp spclk spsdi spsdo bd00 bd01 bd02 bd03 bd04 bd05 bd06 bd07 r10 51k ? r9 51k ? r16 10k ? r42 49.9k ? r43 49.9k ? rc0603 rc0603 rc0603 rc1206 cc0603 c70 0.1 f jp8 jp4 jp28 jp13 jp15 jp16 jp14 jp36 jp38 jp17 jp29 jp30 agnd; 3, 4, 5 t3 out 2 j37 j35 3 t2 s3 o1n o1p o2n o2p s4 out1 agnd; 3, 4, 5 t1-1t 2 1 4 5 6 3 t1-1t 2 1 8 9 10 4 5 6 c70 0.1 f r12 51k ? r11 51k ? r17 10k ? rc0603 rc0603 rc0603 cc0603 iq spsdo jp46 jp47 u4 dvdd; 14 dgnd; 7 74vcx86 02857-b-106 figure 106. ad9773 clock, power supplies, and output circuitry
ad9773 rev. b | page 53 of 60 02857-b-107 j clk k clr pre q q 74lcx112 u7 14 agnd; 8 dvdd; 16 c52 4.7 f 6.3v dvdd c53 0.1 f cc0805 acase 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-a ribbon j1 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp8 dnp rp6 50 ? 2 1 345678910 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp7 dnp rp5 50 ? ad15 ad14 ad13 ad12 ad11 ad10 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 116 215 314 413 512 611 710 89 116 215 314 413 512 611 710 89 rp1 22 ? rp1 22 ? rp1 22 ? rp1 22 ? rp1 22 ? rp1 22 ? rp1 22 ? rp1 22 ? rp2 22 ? rp2 22 ? rp2 22 ? rp2 22 ? rp2 22 ? rp2 22 ? rp2 22 ? rp2 22 ? r15 220 ? rc1206 adclk 74vcx86 j clk k clr pre q q dvdd opclk_2 dvdd; 14 agnd; 7 74lcx112 u7 opclk u4 2 3 1 opclk_3 3 1 2 5 4 10 10 11 12 13 9 7 15 6 c31 4.7 f 6.3v dvdd c34 0.1 f cc0805 acase c30 4.7 f 6.3v dvdd c33 0.1 f cc0805 acase 74vcx86 dvdd; 14 agnd; 7 u4 5 6 4 74vcx86 dvdd; 14 agnd; 7 u3 2 3 1 74vcx86 dvdd; 14 agnd; 7 u3 5 6 4 74vcx86 dvdd; 14 agnd; 7 u3 10 8 9 cx2 cx3 cx1 figure 107. ad9773 evaluation board input (a channel) and clock buffer circuitry
ad9773 rev. b | page 54 of 60 02857-b-108 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 data-b ribbon j2 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp10 dnp rp11 50 ? 2 1 345678910 2 1 345678910 r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r2 r3 r4 r5 r6 r7 r8 r9 rcom rcom rp9 dnp rp12 50 ? bd15 bd14 bd13 bd12 bd11 bd10 bd09 bd08 bd07 bd06 bd05 bd04 bd03 bd02 bd01 bd00 116 215 314 413 512 611 710 89 116 215 314 413 512 611 710 89 rp3 22 ? rp3 22 ? rp3 22 ? rp3 22 ? rp3 22 ? rp3 22 ? rp3 22 ? rp3 22 ? rp4 22 ? rp4 22 ? rp4 22 ? rp4 22 ? rp4 22 ? rp4 22 ? rp4 22 ? rp4 22 ? r21 dnp clkvdd cgnd; 5 clkvdd; 8 aclkx r13 120 ? r4 120 ? r18 200 ? r14 200 ? rc0805 mc100ept22 rc0805 rc0805 rc0805 c43 4.7 f 6.3v dvdd c51 0.1 f c44 4.7 f 6.3v dvdd dgnd; 7 dvdd; 14 u5 74ac14 1 2 dgnd; 7 dvdd; 14 u5 74ac14 12 13 dgnd; 7 dvdd; 14 u5 74ac14 43 dgnd; 7 dvdd; 14 u5 74ac14 10 11 dgnd; 7 dvdd; 14 u5 74ac14 65 dgnd; 7 dvdd; 14 u5 74ac14 89 1 2 3 4 5 6 spi port p1 spcsb spclk spsdi spsdo dgnd; 7 dvdd; 14 u6 74ac14 1 2 dgnd; 7 dvdd; 14 u6 74ac14 13 12 dgnd; 7 dvdd; 14 u6 74ac14 3 4 dgnd; 7 dvdd; 14 u6 74ac14 11 10 dgnd; 7 dvdd; 14 u6 74ac14 5 6 dgnd; 7 dvdd; 14 u6 74ac14 9 8 r50 9k ? r48 9k ? r45 9k ? rc0805 rc0805 rc0805 acase cc805 acase c50 0.1 f cc805 c60 0.1 f c49 4.7 f 6.3v clkdd acase cc805 4 3 6 u8 2 1 7 u8 cc805 c47 1nf cc805 jp41 jp42 c46 0.1 f r20 dnp rc0805 r22 dnp r24 dnp rc0805 rc0805 rc0805 cc805 c48 1nf clkvdd; 8 cgnd; 5 mc100ept22 clkvdd clkvdd clkn clkp + c c c c c + + figure 108. ad9773 evaluation board input (b channel) and spi port circuitry
ad9773 rev. b | page 55 of 60 02857-b-109 figure 109. ad9773 evaluation board components, top side 02857-b-110 figure 110. ad9773 evaluation board components, bottom side
ad9773 rev. b | page 56 of 60 02857-b-111 figure 111. ad9773 evaluation board layout, layer one (top) 02857-b-112 figure 112. ad9773 evaluation board layout, layer two (ground plane)
ad9773 rev. b | page 57 of 60 02857-b-113 figure 113. ad9773 evaluation board layout, layer three (power plane) 02857-b-114 figure 114. ad9773 evaluation board layout, layer four (bottom)
ad9773 rev. b | page 58 of 60 outline dimensions 0.27 0.22 0.17 0.20 0.09 0.50 bsc gage plane 0.25 7 3.5 0 1.05 1.00 0.95 1 20 21 41 40 60 80 61 pin 1 top view (pins down) 14.00 sq 12.00 sq seating plane 1.20 max 0.75 0.60 0.45 1 20 21 41 40 60 80 61 6.00 sq bottom view coplanarity 0.08 compliant to jedec standards ms-026-add-hd 0.15 0.05 figure 115. 80-lead thin plastic quad flat package, exposed pad [tqfp/ed] (sv-80) ordering guide models temperature range package description package option AD9773BSV ?40c to +85c 80-lead thin plastic quad flatpack (tqfp) sv-80 AD9773BSVrl ?40c to +85c 80-lead thin plastic quad flatpack (tqfp) sv-80 ad9773-eb evaluation board
ad9773 rev. b | page 59 of 60 notes
ad9773 rev. b | page 60 of 60 notes ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02857-0-4/04(b)

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